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A64: Implement SABD

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Lioncash 2018-05-08 16:33:28 -04:00 committed by MerryMage
parent 1e10017f4b
commit f00789e6f7
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -714,7 +714,7 @@ INST(SSHL_2, "SSHL", "0Q001
//INST(SQRSHL_2, "SQRSHL", "0Q001110zz1mmmmm010111nnnnnddddd")
INST(SMAX, "SMAX", "0Q001110zz1mmmmm011001nnnnnddddd")
INST(SMIN, "SMIN", "0Q001110zz1mmmmm011011nnnnnddddd")
//INST(SABD, "SABD", "0Q001110zz1mmmmm011101nnnnnddddd")
INST(SABD, "SABD", "0Q001110zz1mmmmm011101nnnnnddddd")
//INST(SABA, "SABA", "0Q001110zz1mmmmm011111nnnnnddddd")
INST(ADD_vector, "ADD (vector)", "0Q001110zz1mmmmm100001nnnnnddddd")
INST(CMTST_2, "CMTST", "0Q001110zz1mmmmm100011nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -73,6 +73,22 @@ bool TranslatorVisitor::CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd)
return true;
}
bool TranslatorVisitor::SABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = 8 << size.ZeroExtend();
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorSignedAbsoluteDifference(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();