From f2345c1590769a7de52a021de4b0bea70b0c5e9a Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Mon, 1 Feb 2021 19:52:49 +0000
Subject: [PATCH] A64/system: Implement MSR/MRS for NZCV

---
 src/frontend/A64/translate/impl/system.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/frontend/A64/translate/impl/system.cpp b/src/frontend/A64/translate/impl/system.cpp
index d82abafe..6537d760 100644
--- a/src/frontend/A64/translate/impl/system.cpp
+++ b/src/frontend/A64/translate/impl/system.cpp
@@ -21,6 +21,8 @@ enum class SystemRegisterEncoding : u32 {
     FPCR = 0b11'011'0100'0100'000,
     // Floating-point Status Register
     FPSR = 0b11'011'0100'0100'001,
+    // NZCV, Condition Flags
+    NZCV = 0b11'011'0100'0010'000,
     // Read/Write Software Thread ID Register
     TPIDR_EL0 = 0b11'011'1101'0000'010,
     // Read-Only Software Thread ID Register
@@ -103,6 +105,9 @@ bool TranslatorVisitor::MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, I
     case SystemRegisterEncoding::FPSR:
         ir.SetFPSR(X(32, Rt));
         return true;
+    case SystemRegisterEncoding::NZCV:
+        ir.SetNZCVRaw(X(32, Rt));
+        return true;
     case SystemRegisterEncoding::TPIDR_EL0:
         ir.SetTPIDR(X(64, Rt));
         return true;
@@ -139,6 +144,9 @@ bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3
     case SystemRegisterEncoding::FPSR:
         X(32, Rt, ir.GetFPSR());
         return true;
+    case SystemRegisterEncoding::NZCV:
+        X(32, Rt, ir.GetNZCVRaw());
+        return true;
     case SystemRegisterEncoding::TPIDR_EL0:
         X(64, Rt, ir.GetTPIDR());
         return true;