From f58aba9871e00fa276a6f5dcae4f725e8b79ddd2 Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Sat, 10 Feb 2018 23:28:05 +0000
Subject: [PATCH] A64: Implement SIMD instruction SSHR, vector variant

---
 src/frontend/A64/decoder/a64.inc              |  2 +-
 .../impl/simd_shift_by_immediate.cpp          | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 038339e0..71579228 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -778,7 +778,7 @@ INST(MOVI,                   "MOVI, MVNI, ORR, BIC (vector, immediate)",  "0Qo01
 //INST(FMOV_2,                 "FMOV (vector, immediate)",                  "0Q00111100000abc111111defghddddd")
 
 // Data Processing - FP and SIMD - SIMD Shift by immediate
-//INST(SSHR_2,                 "SSHR",                                      "0Q0011110IIIIiii000001nnnnnddddd")
+INST(SSHR_2,                 "SSHR",                                      "0Q0011110IIIIiii000001nnnnnddddd")
 //INST(SSRA_2,                 "SSRA",                                      "0Q0011110IIIIiii000101nnnnnddddd")
 //INST(SRSHR_2,                "SRSHR",                                     "0Q0011110IIIIiii001001nnnnnddddd")
 //INST(SRSRA_2,                "SRSRA",                                     "0Q0011110IIIIiii001101nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
index 55627710..62647d47 100644
--- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
+++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
@@ -9,6 +9,25 @@
 
 namespace Dynarmic::A64 {
 
+bool TranslatorVisitor::SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
+    if (immh == 0b0000) {
+        return DecodeError();
+    }
+    if (immh.Bit<3>() && !Q) {
+        return ReservedValue();
+    }
+    const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
+    const size_t datasize = Q ? 128 : 64;
+
+    const u8 shift_amount = static_cast<u8>(2 * esize) - concatenate(immh, immb).ZeroExtend<u8>();
+
+    const IR::U128 operand = V(datasize, Vn);
+    const IR::U128 result = ir.VectorArithmeticShiftRight(esize, operand, shift_amount);
+
+    V(datasize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
     if (immh == 0b0000) {
         return DecodeError();