diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index a1c0e0ad..e22bcde4 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -397,7 +397,7 @@ INST(FCVTPU_2,               "FCVTPU (vector)",                           "01111
 //INST(FCVTZU_int_1,           "FCVTZU (vector, integer)",                  "0111111011111001101110nnnnnddddd")
 INST(FCVTZU_int_2,           "FCVTZU (vector, integer)",                  "011111101z100001101110nnnnnddddd")
 //INST(FRSQRTE_1,              "FRSQRTE",                                   "0111111011111001110110nnnnnddddd")
-//INST(FRSQRTE_2,              "FRSQRTE",                                   "011111101z100001110110nnnnnddddd")
+INST(FRSQRTE_2,              "FRSQRTE",                                   "011111101z100001110110nnnnnddddd")
 
 // Data Processing - FP and SIMD - Scalar three same extra
 //INST(SQRDMLAH_vec_1,         "SQRDMLAH (vector)",                         "01111110zz0mmmmm100001nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
index 0a443aca..a86cca57 100644
--- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
@@ -148,6 +148,16 @@ bool TranslatorVisitor::FCVTZU_int_2(bool sz, Vec Vn, Vec Vd) {
     return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Unsigned);
 }
 
+bool TranslatorVisitor::FRSQRTE_2(bool sz, Vec Vn, Vec Vd) {
+    const size_t esize = sz ? 64 : 32;
+
+    const IR::U32U64 operand = V_scalar(esize, Vn);
+    const IR::U32U64 result = ir.FPRSqrtEstimate(operand);
+
+    V_scalar(esize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::NEG_1(Imm<2> size, Vec Vn, Vec Vd) {
     if (size != 0b11) {
         return ReservedValue();