diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 1327e8c3..4f998673 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -700,7 +700,7 @@ INST(RSUBHN, "RSUBHN, RSUBHN2", "0Q101 //INST(UMULL_vec, "UMULL, UMULL2 (vector)", "0Q101110zz1mmmmm110000nnnnnddddd") // Data Processing - FP and SIMD - SIMD three same -//INST(SHADD, "SHADD", "0Q001110zz1mmmmm000001nnnnnddddd") +INST(SHADD, "SHADD", "0Q001110zz1mmmmm000001nnnnnddddd") //INST(SQADD_2, "SQADD", "0Q001110zz1mmmmm000011nnnnnddddd") //INST(SRHADD, "SRHADD", "0Q001110zz1mmmmm000101nnnnnddddd") //INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index 4e586d9d..33c6004a 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -183,6 +183,22 @@ bool TranslatorVisitor::RSUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { + if (size == 0b11) { + return ReservedValue(); + } + + const size_t datasize = Q ? 128 : 64; + const size_t esize = 8 << size.ZeroExtend(); + + const IR::U128 operand1 = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vm); + const IR::U128 result = ir.VectorHalvingAddSigned(esize, operand1, operand2); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { if (size == 0b11 && !Q) return ReservedValue(); const size_t esize = 8 << size.ZeroExtend();