From fbdae61c1391f74f75173bd0066c422a7dd6edb2 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Thu, 18 Jun 2020 21:58:17 -0400 Subject: [PATCH] A32: Implement ASIMD VMVN (register) Fairly straightforward --- src/frontend/A32/decoder/asimd.inc | 2 +- .../translate/impl/asimd_two_regs_misc.cpp | 19 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 99d0738a..402842be 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -81,7 +81,7 @@ INST(asimd_VREV, "VREV{16,32,64}", "111100111D11zz00dddd000 INST(asimd_VCLS, "VCLS", "111100111D11zz00dddd01000QM0mmmm") // ASIMD INST(asimd_VCLZ, "VCLZ", "111100111D11zz00dddd01001QM0mmmm") // ASIMD INST(asimd_VCNT, "VCNT", "111100111D11zz00dddd01010QM0mmmm") // ASIMD -//INST(asimd_VMVN_reg, "VMVN_reg", "111100111-11--00----01011x-0----") // ASIMD +INST(asimd_VMVN_reg, "VMVN_reg", "111100111D11zz00dddd01011QM0mmmm") // ASIMD //INST(asimd_VPADAL, "VPADAL", "111100111-11--00----0110xx-0----") // ASIMD INST(asimd_VQABS, "VQABS", "111100111D11zz00dddd01110QM0mmmm") // ASIMD INST(asimd_VQNEG, "VQNEG", "111100111D11zz00dddd01111QM0mmmm") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index 6588a295..d6294012 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -133,6 +133,25 @@ bool ArmTranslatorVisitor::asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool return true; } +bool ArmTranslatorVisitor::asimd_VMVN_reg(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { + if (sz != 0b00) { + return UndefinedInstruction(); + } + + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + + const auto reg_m = ir.GetVector(m); + const auto result = ir.VectorNot(reg_m); + + ir.SetVector(d, result); + return true; +} + bool ArmTranslatorVisitor::asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { if (sz == 0b11) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index d3ca8015..0f772839 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -466,6 +466,7 @@ struct ArmTranslatorVisitor final { bool asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); + bool asimd_VMVN_reg(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VQNEG(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);