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Author SHA1 Message Date
MerryMage
5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage
90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage
98bd7ff6a5 Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support. 2016-07-20 12:08:17 +01:00
Merry
95316b8443 Merged in Subv/dynarmic/arm_mem_tests (pull request #4) 
Added some fuzz tests for most cases of ARM Load/Store instructions
 2016-07-20 10:19:55 +01:00
MerryMage
95588d3faa Fix Thumb BLX (imm), BL (imm) for negative immediates 2016-07-18 22:48:23 +01:00
MerryMage
3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
Subv
fce8f75077 Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC. 2016-07-18 16:13:33 -05:00
Subv
426ffc9971 Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH. 
These tests do not test the behavior of writing to the PC.
 2016-07-18 16:13:02 -05:00
Subv
c330d9e0e3 Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests. 2016-07-18 16:10:35 -05:00
MerryMage
e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
Subv
ccc61472b9 Added format strings for ARM STRBT encodings A1 and A2 2016-07-18 14:20:58 -05:00
Subv
8617bf80a1 Added format strings for ARM LDRBT encodings A1 and A2 2016-07-18 14:18:39 -05:00
Subv
5d5ea9325c Added format strings for ARM STRT encodings A1 and A2 2016-07-18 14:05:53 -05:00
MerryMage
2363759c62 Implement thumb STM, LDM. Fix thumb POP implementation for P=1. 2016-07-18 20:05:35 +01:00
MerryMage
8a310777a1 backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC 2016-07-18 20:01:48 +01:00
Subv
77761ba032 Added the format strings for LDRT encodings A1 and A2. 2016-07-18 14:01:18 -05:00
MerryMage
14dcb18bbe Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2) 2016-07-18 18:48:08 +01:00
MerryMage
a605a43ef9 Implement Thumb Instructions: STRH (imm), LDRH (imm) 2016-07-18 18:28:52 +01:00
MerryMage
f9755870bb Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg) 2016-07-18 18:02:02 +01:00
Merry
3b8790bf29 Merged in Subv/dynarmic/small_opt (pull request #3) 
Pass the current IR::Block by reference to the emitter.
 2016-07-18 17:38:12 +01:00
MerryMage
dfef65d98f Implement thumb POP instruction 2016-07-18 17:37:48 +01:00
Subv
703a46ec99 Pass the current IR::Block by reference to the emitter. 
This avoids calling the copy constructor more times than needed.
 2016-07-18 11:27:33 -05:00
MerryMage
f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage
9109b226af Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm) 2016-07-18 11:16:12 +01:00
MerryMage
c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
MerryMage
bf99ddd065 Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic 2016-07-18 10:33:52 +01:00
MerryMage
28a201da16 Implement Thumb ADR instruction 2016-07-18 09:25:33 +01:00
Merry
6708960aeb Merged in Subv/dynarmic/rev (pull request #2) 
Implemented ARM REV and REVSH instructions, with tests.
 2016-07-17 22:13:36 +01:00
Subv
0cdf5fe751 Implemented ARM REV and REVSH instructions, with tests. 2016-07-17 14:45:42 -05:00
Merry
24aa24b1bc Merged in Subv/dynarmic (pull request #1) 
Implemented ARM CMP (imm) instruction.
 2016-07-17 19:43:49 +01:00
Subv
7f09510945 Implemented ARM CMP (imm) instruction. 2016-07-17 13:29:37 -05:00
MerryMage
3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} 2016-07-16 19:23:42 +01:00
MerryMage
866dce0f23 tests/Thumb: Add revsh (thumb) test 2016-07-16 19:22:57 +01:00
MerryMage
22b1bd7cc7 tests/Skyeye: Fix thumb REVSH translation 2016-07-16 19:22:09 +01:00
MerryMage
3ef9da9a92 Docs: Design documentation 2016-07-15 16:47:13 +01:00
MerryMage
4b1c27e64f Implement arm_ADC_imm 2016-07-14 20:02:41 +01:00
MerryMage
63242924fc Implement thumb16_SVC 2016-07-14 15:01:30 +01:00
MerryMage
181f78f36e Common: Remove src/common/logging/log.* 2016-07-14 14:55:08 +01:00
MerryMage
07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
MerryMage
9b2aff166a Implement arm_SVC 2016-07-14 14:29:46 +01:00
MerryMage
672ffb93d0 frontend/translator: Skeleton for Arm translator 2016-07-14 13:28:20 +01:00
MerryMage
7d7751c157 Allow IR blocks to require a cond for block entry. 
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
 2016-07-14 12:52:53 +01:00
MerryMage
4ab4ca58f9 backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight 2016-07-14 09:02:27 +01:00
MerryMage
08e848044d backend_x64: Inline Routines::GenReturnFromRunCode into emitted code 2016-07-12 16:46:27 +01:00
MerryMage
619b451902 clang support 2016-07-12 14:31:43 +01:00
MerryMage
8449deb0bc MSVC support 2016-07-12 13:28:09 +01:00
MerryMage
44352680c6 s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones 2016-07-12 11:09:34 +01:00
MerryMage
6e46e7899a Translate/Thumb: Fallback to interpreter for Thumb32 instructions 2016-07-12 11:02:45 +01:00
MerryMage
60455f9bbc tests/fuzz_thumb: Fuzz instructions that may change the PC 2016-07-12 10:58:57 +01:00
MerryMage
09420d190b IR: Implement IR microinstructions ALUWritePC and LoadWritePC 2016-07-12 10:58:14 +01:00