MerryMage
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b3bb1d5048
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Tests: Tidy up ARM fuzz tests
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2016-08-07 21:55:38 +01:00 |
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MerryMage
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4dcd1d1859
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Arm: BLX is UNPREDICTABLE when Rm is PC
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2016-08-07 20:50:33 +01:00 |
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MerryMage
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1af5bef32c
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TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
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2016-08-07 20:40:31 +01:00 |
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MerryMage
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3a465ba4a8
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VFP: Implement VLDR
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2016-08-07 19:59:35 +01:00 |
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MerryMage
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a2c2db277b
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VFP: Implement VMOV (all variants)
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2016-08-07 19:25:12 +01:00 |
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Tillmann Karras
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55204a80d0
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Implement SMMLA, SMMLS, SMMUL
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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81d9d4b012
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Add Subv's sign/zero extension tests
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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a281fcc744
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Fix printf
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2016-08-06 21:17:11 +01:00 |
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MerryMage
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9ab7626374
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Tests/VFP: Add tests for VADD.F32
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2016-08-06 20:03:15 +01:00 |
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MerryMage
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4b31ea25a7
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VFP: Implement VADD.{F32,F64}
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2016-08-06 20:03:15 +01:00 |
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bunnei
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a5e2116e12
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fuzz_arm: Log write records on failure.
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2016-08-05 20:04:57 -04:00 |
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MerryMage
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640ce48baa
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VFP: Implement {Get,Set}ExtendedRegister{32,64}
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2016-08-05 19:06:10 +01:00 |
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MerryMage
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6f6f60c61b
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tests/FuzzArm: Only call raise(SIGTRAP) when __unix__ is defined
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2016-08-05 16:04:16 +01:00 |
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Tillmann Karras
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eb2e6e8bea
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Implement some multiplies
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2016-08-05 02:09:54 +01:00 |
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Tillmann Karras
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a97668ead4
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Simplify ARM fuzz tests
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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023643b4fa
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Disable load/store tests for now
I don't feel like debugging that right now.
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2016-08-05 02:09:27 +01:00 |
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Tillmann Karras
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ab383b4be5
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Break tests by fixing them
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2016-08-05 02:08:41 +01:00 |
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Tillmann Karras
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af27ef8d6c
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Optionally disassemble x86_64 code using LLVM
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2016-08-05 02:08:41 +01:00 |
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Tillmann Karras
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dacaeadb6a
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Raise SIGTRAP on non-Windows
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2016-08-03 00:44:08 +01:00 |
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MerryMage
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64c17a2489
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tests/FuzzArm: Print out IR upon failure
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2016-08-02 13:48:06 +01:00 |
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MerryMage
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5fbfc6c155
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Implement some simple IR optimizations (get/set eliminiation and DCE)
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2016-07-21 21:48:45 +01:00 |
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Subv
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fce8f75077
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Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC.
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2016-07-18 16:13:33 -05:00 |
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Subv
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426ffc9971
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Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH.
These tests do not test the behavior of writing to the PC.
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2016-07-18 16:13:02 -05:00 |
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Subv
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c330d9e0e3
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Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests.
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2016-07-18 16:10:35 -05:00 |
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MerryMage
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dfef65d98f
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Implement thumb POP instruction
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2016-07-18 17:37:48 +01:00 |
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MerryMage
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c18a3eeab4
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Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
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2016-07-18 10:38:22 +01:00 |
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Subv
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0cdf5fe751
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Implemented ARM REV and REVSH instructions, with tests.
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2016-07-17 14:45:42 -05:00 |
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MerryMage
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866dce0f23
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tests/Thumb: Add revsh (thumb) test
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2016-07-16 19:22:57 +01:00 |
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MerryMage
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4b1c27e64f
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Implement arm_ADC_imm
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2016-07-14 20:02:41 +01:00 |
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MerryMage
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07eaf100ba
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Reorganise src/frontend: Add subdirectories disassembler and translate
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2016-07-14 14:39:43 +01:00 |
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MerryMage
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8449deb0bc
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MSVC support
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2016-07-12 13:28:09 +01:00 |
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MerryMage
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65d27f3486
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tests: Add some Arm tests
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2016-07-12 09:12:56 +01:00 |
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