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166 commits

Author SHA1 Message Date
MerryMage
dc26afbd7e translate_arm: Translate more than one conditional instruction in a block 2016-08-25 13:05:33 +01:00
Lioncash
1395baefa9 interface: Return register files by const reference 
Prevents unnecessary copies where they aren't particularly required.
 2016-08-25 12:51:41 +01:00
MerryMage
22cca5ff72 emit_x64: Actually advance RSB pointer 2016-08-24 23:19:47 +01:00
Lioncash
eba3a06d80 frontend: Introduce FPSCR register helper class 
Encapsulates all of the FPSCR state.
 2016-08-24 20:51:14 +01:00
MerryMage
b5a86889cd Implement VCVT 2016-08-23 22:20:04 +01:00
MerryMage
c8b2f63c93 get_set_elimination_pass: Eliminate unnecessary gets/sets of extended registers 2016-08-23 15:57:20 +01:00
MerryMage
8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
MerryMage
72250b119f backend_x64/block_of_code: Add more floating point constants 
* MFloatPositiveZero32
* MFloatPositiveZero64
* MFloatMinS32
* MFloatMaxS32
* MFloatMinU32
* MFloatMaxU32
 2016-08-22 15:54:19 +01:00
Lioncash
1abe881921 basic_block: Add proxy member functions for the instruction list 
Currently basic block kind of acts like a 'dumb struct' which makes things
a little more verbose to write (as opposed to keeping it all in one place,
I guess). It's also a little wonky conceptually, considering a block is
composed of instructions (i.e. 'contains' them).

So providing accessors that make it act more like a container can make working
with algorithms a little nicer. It also makes the API a little more
defined.

Ideally, the list would be only available through a function, but
currently, the pool allocator is exposed, which seems somewhat odd,
considering the block itself should manage its overall allocations
(with placement new, and regular new), rather than putting that
sanitizing directly on the IR emitter (it should just care about emission,
not block state). However, recontaining that can be followed up with,
as it's very trivial to do.
 2016-08-22 13:44:56 +01:00
Lioncash
86f803da04 reg_alloc: Use Inst's HasUses() function where applicable 2016-08-20 21:26:09 +01:00
Lioncash
36a0ad5bc2 reg_alloc: const correctness for ValueLocation() 2016-08-19 19:33:57 +01:00
MerryMage
2d6a86e43c Remove <cassert> 2016-08-19 01:53:24 +01:00
MerryMage
269160ef0d emit_x64: Clear RSB-related caches when ClearCache() is called 2016-08-18 18:18:44 +01:00
MerryMage
1a3f3ac435 emit_x64: Correct behaviour of PackedOperation for immediate argument 
x64 MOVD_xmm does not support an immediate oparg
 2016-08-18 18:17:17 +01:00
MerryMage
b2de47954b EmitX64: Emit correct cycle count on cond failure 2016-08-18 18:16:18 +01:00
Lioncash
841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00
Lioncash
cbd99e4367 jitstate: Use std::array's fill() in ResetRSB 
Performs the equivalent behavior
 2016-08-17 10:10:43 +01:00
Lioncash
74ee92ee38 jitstate: const correctness 
GetReturnFromRunCodeAddress is const qualified, so this can accept a const
pointer. This also allows for making the constructor accept a const
pointer as well.
 2016-08-17 10:10:43 +01:00
Lioncash
439619c827 reg_alloc: Make GetRegLoc return by const reference 
Considering a HostLocInfo instance houses a std::vector, every time this
function is called can cause a potential heap allocation.

This can be somewhat unnecessary because this function is only used to query
for information we already have.

Considering this is used by several other internal query functions such as
IsRegisterOccupied, IsRegisterAllocated, and IsLastUse, this will result
in better codegen (returning an address is just 3 instructions excluding
the ret instruction for returning, meanwhile heap alloc can be 60+).

This also renames the function to have the same name as its non-const
counterpart, since overloading will just select the correct function
instead of putting that onus on the developer.
 2016-08-17 10:08:08 +01:00
MerryMage
0ebb572e2d Optimization: Make RSB a ring buffer instead of a stack 2016-08-15 15:48:22 +01:00
MerryMage
7d7ac0af71 Optimization: Make SVC use RSB 2016-08-15 15:02:08 +01:00
MerryMage
6c45619aa1 Optimization: Implement terminal LinkBlockFast 2016-08-15 14:33:17 +01:00
MerryMage
624e84fa09 Optimization: Tweak RSB 2016-08-15 14:08:06 +01:00
MerryMage
070298b948 Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect 2016-08-15 13:21:58 +01:00
MerryMage
e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
MerryMage
8fc21f481a RegAlloc: Handle case when def is unused 2016-08-13 01:55:03 +01:00
MerryMage
d43d97b990 EmitX64/EmitPushRSB: Assert that patch location is of correct size 2016-08-13 00:52:31 +01:00
MerryMage
960d14d18e Optimization: Implement Return Stack Buffer 2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage
1029fd27ce Update documentation (2016-08-12) 2016-08-12 18:17:31 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage
29d30bf931 Interface: Added Jit::Reset to reset CPU state 2016-08-09 22:45:54 +01:00
Tillmann Karras
5d26899ac9 Add simplified LogicalShiftRight64 IR opcode 2016-08-08 22:27:05 +01:00
Tillmann Karras
ccb2aa96a5 Add support for the APSR.Q flag 2016-08-08 22:27:04 +01:00
MerryMage
975f011fc0 BackendX64/RegAlloc: Do not allocate RSP for guest use 2016-08-08 16:01:07 +01:00
MerryMage
abd113f160 EmitX64: Renamed patch_jmp_locations to patch_jg_locations 2016-08-08 15:56:07 +01:00
MerryMage
52fa998e6b EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags 2016-08-07 22:47:43 +01:00
MerryMage
04c1a0d2de EmitX64: Switch MXCSR when switching to interpreter 2016-08-07 22:47:17 +01:00
MerryMage
a32063fa60 EmitX64: Implement block linking 2016-08-07 22:11:39 +01:00
MerryMage
328422b740 RegAlloc: HostCall flushes all XMM regsiters 2016-08-07 21:02:16 +01:00
MerryMage
a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage
aba705f6b9 BackendX64: Merge Routines into BlockOfCode 2016-08-07 18:08:48 +01:00
MerryMage
0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage
3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage
f88b1b4c2e FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask 2016-08-07 01:10:19 +01:00
Tillmann Karras
9264e2e04c Use XOR when loading a zero immediate 2016-08-06 21:17:11 +01:00
Tillmann Karras
846d07d7b5 Add Sub64 opcode 2016-08-06 21:17:11 +01:00
Tillmann Karras
b9f4f1ed0f Add carry support to MostSignificantWord 2016-08-06 21:17:11 +01:00
MerryMage
411e804b0d Interface: Forward declare Arm::LocationDescriptor 2016-08-06 20:11:35 +01:00
MerryMage
4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage
94d5738f62 BackendX64/Routines: Add floating-point constants 2016-08-06 20:01:47 +01:00
MerryMage
8754728a82 BackendX64/RegAlloc: Corrected code emitted by EmitMove for XMM->Spill case 2016-08-06 20:01:47 +01:00
MerryMage
8cc4fe8a10 BackendX64/RegAlloc: HostLocToX64 now handles XMM registers properly 2016-08-06 20:01:47 +01:00
MerryMage
856298577d EmitX64: Don't give MOVSX or MOVZX an immediate oparg 2016-08-06 01:03:39 +01:00
MerryMage
640ce48baa VFP: Implement {Get,Set}ExtendedRegister{32,64} 2016-08-05 19:06:10 +01:00
MerryMage
4c0a85f3b3 EmitX64: Correct EmitPack2x32To1x64 implementation 2016-08-05 18:43:24 +01:00
MerryMage
742eeb8913 BackendX64/RegAlloc: Correct debugging asserts and correct UseDef behaviour for spill locations 2016-08-05 18:43:22 +01:00
MerryMage
d80dcc5367 BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64 2016-08-05 15:27:29 +01:00
MerryMage
2b025183a2 BackendX64/RegAlloc: Correct UseDefRegsiter behaviour for last use 2016-08-05 15:24:25 +01:00
MerryMage
b4aa01ccf4 Merge remote-tracking branch 'tilkax/master' 2016-08-05 14:14:06 +01:00
MerryMage
94e75ad32f BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg} 2016-08-05 14:11:27 +01:00
MerryMage
92bd5f214b BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg 2016-08-05 14:10:39 +01:00
MerryMage
ca40015145 IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint) 2016-08-05 14:07:27 +01:00
Tillmann Karras
72c503016c Fix Pack2x32To1x64 
Not sure how to fix this properly.
 2016-08-05 02:09:30 +01:00
Tillmann Karras
3fdc093d10 Add more IR opcodes for multiply instructions 
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
 2016-08-05 02:09:30 +01:00
Tillmann Karras
af27ef8d6c Optionally disassemble x86_64 code using LLVM 2016-08-05 02:08:41 +01:00
Tillmann Karras
2488926341 Add IR opcode RotateRightExtended 
to rotate through the carry flag
 2016-08-03 00:47:16 +01:00
Tillmann Karras
306e070ab5 Use opcodes.inc for emit_x64.h 2016-08-03 00:44:08 +01:00
MerryMage
1252bd653d RegAlloc: Define constructors for HostLocInfo to make MSVC happy 2016-08-03 00:25:42 +01:00
MerryMage
4414ec5bc8 RegAlloc: Allow allocation of XMM registers 2016-08-02 13:46:12 +01:00
MerryMage
864081d1a0 BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR 2016-08-02 12:00:11 +01:00
MerryMage
93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage
be87038ffd IROpt: Port get/set elimination pass to current IR 2016-08-02 11:51:05 +01:00
MerryMage
51448aa06d More Speed 2016-07-22 23:55:00 +01:00
MerryMage
5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage
90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage
3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
MerryMage
e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
MerryMage
8a310777a1 backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC 2016-07-18 20:01:48 +01:00
Subv
703a46ec99 Pass the current IR::Block by reference to the emitter. 
This avoids calling the copy constructor more times than needed.
 2016-07-18 11:27:33 -05:00
MerryMage
f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage
c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
MerryMage
3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} 2016-07-16 19:23:42 +01:00
MerryMage
07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
MerryMage
9b2aff166a Implement arm_SVC 2016-07-14 14:29:46 +01:00
MerryMage
7d7751c157 Allow IR blocks to require a cond for block entry. 
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
 2016-07-14 12:52:53 +01:00
MerryMage
4ab4ca58f9 backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight 2016-07-14 09:02:27 +01:00
MerryMage
08e848044d backend_x64: Inline Routines::GenReturnFromRunCode into emitted code 2016-07-12 16:46:27 +01:00
MerryMage
619b451902 clang support 2016-07-12 14:31:43 +01:00
MerryMage
8449deb0bc MSVC support 2016-07-12 13:28:09 +01:00
MerryMage
09420d190b IR: Implement IR microinstructions ALUWritePC and LoadWritePC 2016-07-12 10:58:14 +01:00
MerryMage
1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg 2016-07-11 23:11:05 +01:00
MerryMage
e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 2016-07-11 22:43:53 +01:00
MerryMage
cbcf61a9e6 backend_x64/RegAlloc: Provide convenience function HostCall to save registers necessary as per host ABI 2016-07-11 15:28:10 +01:00