MerryMage
|
6eb069e80d
|
fp: Implement FPRSqrtStepFused
|
2020-04-22 20:46:22 +01:00 |
|
Lioncash
|
c704acafe4
|
A64: Implement FMUL (by element)'s scalar double/single-precision variant
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
e199887fbc
|
fp: Implement FPMulAdd
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
bde58b04d4
|
IR: Implement FPRSqrtEstimate
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
b53127600b
|
fp: A64::FPCR -> FP::FPCR
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
e24054f4d7
|
fp: Implement FPRoundInt
|
2020-04-22 20:46:20 +01:00 |
|
MerryMage
|
f876e4afa2
|
fp: Implement FPProcessNaN
|
2020-04-22 20:46:20 +01:00 |
|
MerryMage
|
797e18cd97
|
fp: Move FPToFixed to its own file
|
2020-04-22 20:46:20 +01:00 |
|
MerryMage
|
9571269552
|
fp/op: Implement FPToFixed
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
8087e8df05
|
mantissa_util: Implement ResidualErrorOnRightShift
Accurately calculate residual error that is shifted out
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
7360a2579b
|
mp: Implement metaprogramming library
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
4ab029c114
|
fp: Implement FPUnpack
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
4875658917
|
fp: Implement FPProcessException
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
3cb98e1560
|
fp: Move fp_util to fp/util
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
c41a38b13e
|
fp: Add FPSR
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
66381352f3
|
fp: Add FPInfo
Provides information about floating-point format for various bit sizes
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
d21659152c
|
safe_ops: Implement safe shifting operations
Implement shifiting operations that perform consistently across architectures
without running into undefined or implemented-defined behaviour.
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
8651c2d10e
|
u128: Implement u128
For when we need a 128-bit integer
|
2020-04-22 20:46:19 +01:00 |
|
Lioncash
|
a1d6a86e8c
|
A64: Implement ADDV
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
d875c08ebf
|
fp: Extract common RoundingMode enum
|
2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
436ca80bcd
|
Merge branch 'global_monitor'
|
2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
57f7c7e1b0
|
Implement global exclusive monitor
|
2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
2fc6b33829
|
CMakeLists: Add missing files
|
2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
593eca7fb1
|
A64: Implement load/store single structure instructions
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
|
2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
8c90fcf58e
|
IR: Implement FPMulAdd
|
2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
b312d28295
|
ir: Add an opcode for doing an SM4 lookup table query
|
2020-04-22 20:46:17 +01:00 |
|
MerryMage
|
a86d4093cd
|
A64: Implement MLA (by element)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
870e418b0b
|
A64: Implement SHL (scalar)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
769373b3ed
|
A64: Implement SM3TT1A
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
cf81f04ed3
|
A64: Implement RAX1
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
78a047f0f9
|
A64: Implement EXT
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
8bba37089e
|
A64: Implement UADDW
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
94f0fba16b
|
A64: Implement SHA1H
This is a fairly trivial instruction it's essentially:
result = ROL(data, 30);
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
6177c2c63d
|
CMakeLists: Add fp_util, macro_util and math_util headers
Allows the headers to show up within IDEs
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
7a66224d9a
|
A64: Implement EOR3 and BCAX
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
fd8f4c1195
|
A64: Implement UCVTF (vector, integer), scalar variant
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
be57608353
|
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
bd2b415850
|
A64: Implement ADDP (scalar)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e97581d063
|
fuzz_with_unicorn: Print AArch64 disassembly
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5edd623b9d
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f378d2ef1b
|
Forward declare IR::Opcode and IR::Type where possible
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e858ce0b35
|
A64: Implement SIMD instructions XTN, XTN2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1d0cd95b23
|
A64: Implement SIMD instruction SHL
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
afe16fa0f3
|
cast_util: Add BitCast and BitCastPointee
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
35a29a9665
|
A64: Implement ZIP1
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1a7b7b541a
|
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4c5871d5d5
|
A64: Implement ADD (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ef906dbbfa
|
A64: Implement FCCMP
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b02b861242
|
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
|
2020-04-22 20:46:13 +01:00 |
|