Lioncash
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d9fc6cf31f
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A64: Implement SDOT and UDOT's vector variant
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2020-04-22 20:53:45 +01:00 |
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MerryMage
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ff3805e332
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A32/decoders: Split instruction list into include file
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2020-04-22 20:46:23 +01:00 |
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MerryMage
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f9c6d5e1a0
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common: Move all cryptographic function to common/crypto
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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901bd9b4e2
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IR: Implement FPRecipStepFused, FPVectorRecipStepFused
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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c1dcfe29f7
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IR: Implement FPRecipEstimate
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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1edd0125b2
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mp: rename mp.h to mp/function_info.h
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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6eb069e80d
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fp: Implement FPRSqrtStepFused
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2020-04-22 20:46:22 +01:00 |
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Lioncash
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c704acafe4
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A64: Implement FMUL (by element)'s scalar double/single-precision variant
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2020-04-22 20:46:21 +01:00 |
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MerryMage
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e199887fbc
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fp: Implement FPMulAdd
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2020-04-22 20:46:21 +01:00 |
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MerryMage
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bde58b04d4
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IR: Implement FPRSqrtEstimate
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2020-04-22 20:46:21 +01:00 |
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MerryMage
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b53127600b
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fp: A64::FPCR -> FP::FPCR
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2020-04-22 20:46:21 +01:00 |
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MerryMage
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e24054f4d7
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fp: Implement FPRoundInt
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2020-04-22 20:46:20 +01:00 |
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MerryMage
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f876e4afa2
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fp: Implement FPProcessNaN
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2020-04-22 20:46:20 +01:00 |
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MerryMage
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797e18cd97
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fp: Move FPToFixed to its own file
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2020-04-22 20:46:20 +01:00 |
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MerryMage
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9571269552
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fp/op: Implement FPToFixed
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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8087e8df05
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mantissa_util: Implement ResidualErrorOnRightShift
Accurately calculate residual error that is shifted out
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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7360a2579b
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mp: Implement metaprogramming library
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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4ab029c114
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fp: Implement FPUnpack
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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4875658917
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fp: Implement FPProcessException
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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3cb98e1560
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fp: Move fp_util to fp/util
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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c41a38b13e
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fp: Add FPSR
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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66381352f3
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fp: Add FPInfo
Provides information about floating-point format for various bit sizes
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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d21659152c
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safe_ops: Implement safe shifting operations
Implement shifiting operations that perform consistently across architectures
without running into undefined or implemented-defined behaviour.
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2020-04-22 20:46:19 +01:00 |
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MerryMage
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8651c2d10e
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u128: Implement u128
For when we need a 128-bit integer
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2020-04-22 20:46:19 +01:00 |
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Lioncash
|
a1d6a86e8c
|
A64: Implement ADDV
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2020-04-22 20:46:19 +01:00 |
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MerryMage
|
d875c08ebf
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fp: Extract common RoundingMode enum
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2020-04-22 20:46:18 +01:00 |
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MerryMage
|
436ca80bcd
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Merge branch 'global_monitor'
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2020-04-22 20:46:18 +01:00 |
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MerryMage
|
57f7c7e1b0
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Implement global exclusive monitor
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2020-04-22 20:46:18 +01:00 |
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MerryMage
|
2fc6b33829
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CMakeLists: Add missing files
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2020-04-22 20:46:18 +01:00 |
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Lioncash
|
593eca7fb1
|
A64: Implement load/store single structure instructions
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
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2020-04-22 20:46:18 +01:00 |
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MerryMage
|
8c90fcf58e
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IR: Implement FPMulAdd
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2020-04-22 20:46:18 +01:00 |
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Lioncash
|
b312d28295
|
ir: Add an opcode for doing an SM4 lookup table query
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2020-04-22 20:46:17 +01:00 |
|
MerryMage
|
a86d4093cd
|
A64: Implement MLA (by element)
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2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
870e418b0b
|
A64: Implement SHL (scalar)
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2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
769373b3ed
|
A64: Implement SM3TT1A
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2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
cf81f04ed3
|
A64: Implement RAX1
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
78a047f0f9
|
A64: Implement EXT
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
8bba37089e
|
A64: Implement UADDW
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2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
94f0fba16b
|
A64: Implement SHA1H
This is a fairly trivial instruction it's essentially:
result = ROL(data, 30);
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2020-04-22 20:46:15 +01:00 |
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Lioncash
|
6177c2c63d
|
CMakeLists: Add fp_util, macro_util and math_util headers
Allows the headers to show up within IDEs
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
7a66224d9a
|
A64: Implement EOR3 and BCAX
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
fd8f4c1195
|
A64: Implement UCVTF (vector, integer), scalar variant
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
be57608353
|
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
bd2b415850
|
A64: Implement ADDP (scalar)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e97581d063
|
fuzz_with_unicorn: Print AArch64 disassembly
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5edd623b9d
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f378d2ef1b
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Forward declare IR::Opcode and IR::Type where possible
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e858ce0b35
|
A64: Implement SIMD instructions XTN, XTN2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1d0cd95b23
|
A64: Implement SIMD instruction SHL
|
2020-04-22 20:46:13 +01:00 |
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