From 348b764f088bdefcf28644b150ebb3bf2b1946b6 Mon Sep 17 00:00:00 2001
From: Celeste <colean@colean.cc>
Date: Sun, 20 Feb 2022 18:48:59 +0000
Subject: [PATCH] Implement almost all instructions

The only instructions not implemented are sound and display related as well as the RND instruction which will be implemented soon.
---
 Cargo.lock  |  2 +-
 Cargo.toml  |  2 +-
 src/main.rs | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 74 insertions(+), 2 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 97e90f2..65df62f 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -4,4 +4,4 @@ version = 3
 
 [[package]]
 name = "celc8"
-version = "0.1.2"
+version = "0.1.3"
diff --git a/Cargo.toml b/Cargo.toml
index d30037a..2ae6386 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "celc8"
-version = "0.1.2"
+version = "0.1.3"
 edition = "2021"
 
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
diff --git a/src/main.rs b/src/main.rs
index 72016a1..9fcf2d6 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -393,6 +393,78 @@ fn execute(opcode: u16, instruction: Instruction, mut cpu: Cpu) -> Cpu {
 
 		cpu.incrementpc();
 	}
+	else if instruction.name == "SNE_VX_VY" {
+		let register1 = args[0] as usize;
+		let register2 = args[1] as usize;
+
+		if cpu.regread(register1) != cpu.regread(register2) {
+			cpu.incrementpc();
+			cpu.incrementpc();
+		} else {
+			cpu.incrementpc();
+		}
+	}
+	else if instruction.name == "JP_V0_ADDR" { cpu.setpc(*cpu.regread(0) as u16 + args[0] as u16); }
+	else if instruction.name == "LD_I_ADDR" {
+		cpu.iwrite(args[0]);
+		cpu.incrementpc();
+	}
+	else if instruction.name == "LD_VX_DT" {
+		cpu.regwrite(args[0] as usize, cpu.dt);
+		cpu.incrementpc();
+	}
+	else if instruction.name == "LD_DT_VX" {
+		cpu.dt = *cpu.regread(args[0] as usize);
+		cpu.incrementpc();
+	}
+	else if instruction.name == "LD_ST_VX" {
+		cpu.st = *cpu.regread(args[0] as usize);
+		cpu.incrementpc();
+	}
+	else if instruction.name == "ADD_I_VX" {
+		cpu.iwrite(*cpu.iread() + (*cpu.regread(args[0] as usize)) as u16);
+		cpu.incrementpc();
+	}
+	else if instruction.name == "LD_B_VX" {
+		let i = *cpu.iread();
+		let a = args[0] / 100;
+		let b = (args[0] / 10) - (a * 10);
+		let c = args[0] - (a * 100) - (b * 10);
+		
+		cpu.ramwrite(i as usize, a as u8);
+		cpu.ramwrite(i as usize + 1 as usize, b as u8);
+		cpu.ramwrite(i as usize + 2 as usize, c as u8);
+		
+		cpu.incrementpc();
+	}
+	else if instruction.name == "LD_IB_VX" {
+		let i = *cpu.iread();
+		let mut x = 0;
+		let y = args[0];
+		
+		cpu.ramwrite(i as usize, *cpu.regread(0));
+		
+		while x != y {
+			x = x + 1;
+			cpu.ramwrite(i as usize + x as usize, *cpu.regread(x as usize));
+		}
+
+		cpu.incrementpc();
+	}
+	else if instruction.name == "LD_VX_IB" {
+		let i = *cpu.iread();
+		let mut x = 0;
+		let y = args[0];
+		
+		cpu.regwrite(0, *cpu.ramread(i as usize));
+		
+		while x != y {
+			x = x + 1;
+			cpu.regwrite(x as usize, *cpu.ramread(i as usize + x as usize));
+		}
+
+		cpu.incrementpc();
+	}
 	else {
 		println!("Unimplemented instruction {}. Skipping.", instruction.name);
 		cpu.incrementpc();