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authorCeleste <colean@colean.cc>2022-02-15 21:34:00 +0000
committerCeleste <colean@colean.cc>2022-02-15 21:34:00 +0000
commitef41729efb989271c0d8002fcc2b5906f03e8958 (patch)
treec0fd415657dae702d4c4213599b1f7ba6d6a7a1b
parentab04bbcdb65f32f73060e6419b2378ef3b8bc38a (diff)
more stupid stuff
-rw-r--r--src/main.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main.rs b/src/main.rs
index f655269..1fcab06 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -16,11 +16,11 @@ fn main() {
.expect("Registers file not read properly.");
let sreg: Vec<&str> = lreg.split(",").collect();
let mut x = 0;
+ x = x + 1;
for s in sreg {
let c = s.replace("\n","");
let int: i32 = c.parse().unwrap();
registers[x] = int;
- x = x + 1;
}
}