2014-04-09 00:15:46 +01:00
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// Copyright 2014 Citra Emulator Project
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2014-12-17 05:38:14 +00:00
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// Licensed under GPLv2 or any later version
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2014-04-09 00:15:46 +01:00
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// Refer to the license.txt file included.
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2013-09-19 04:52:51 +01:00
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2015-05-06 08:06:12 +01:00
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/swap.h"
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2013-09-19 04:52:51 +01:00
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2015-05-13 02:38:29 +01:00
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#include "core/hle/config_mem.h"
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#include "core/hle/shared_page.h"
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2014-04-09 01:15:08 +01:00
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#include "core/hw/hw.h"
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2015-05-13 02:38:29 +01:00
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#include "core/mem_map.h"
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#include "core/memory.h"
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2013-09-19 04:52:51 +01:00
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namespace Memory {
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template <typename T>
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2014-08-28 19:20:55 +01:00
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inline void Read(T &var, const VAddr vaddr) {
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2014-04-01 23:18:02 +01:00
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// TODO: Figure out the fastest order of tests for both read and write (they are probably different).
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// TODO: Make sure this represents the mirrors in a correct way.
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// Could just do a base-relative read, too.... TODO
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2013-09-19 04:52:51 +01:00
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2014-05-08 02:04:55 +01:00
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// Kernel memory command buffer
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2015-05-09 04:39:56 +01:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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var = *((const T*)&g_tls_mem[vaddr - TLS_AREA_VADDR]);
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2014-04-13 02:55:36 +01:00
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2014-04-30 04:16:12 +01:00
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// ExeFS:/.code is loaded here
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2015-05-09 04:39:56 +01:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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var = *((const T*)&g_exefs_code[vaddr - PROCESS_IMAGE_VADDR]);
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2014-04-30 04:16:12 +01:00
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2014-11-23 03:35:45 +00:00
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// FCRAM - linear heap
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2015-05-09 04:39:56 +01:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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var = *((const T*)&g_heap_linear[vaddr - LINEAR_HEAP_VADDR]);
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2014-04-18 02:15:40 +01:00
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2014-04-18 02:05:34 +01:00
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// FCRAM - application heap
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2014-04-25 04:56:06 +01:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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var = *((const T*)&g_heap[vaddr - HEAP_VADDR]);
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2014-04-17 23:40:42 +01:00
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2014-04-25 04:56:06 +01:00
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// Shared memory
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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var = *((const T*)&g_shared_mem[vaddr - SHARED_MEMORY_VADDR]);
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2014-04-25 04:56:06 +01:00
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2014-05-07 04:32:04 +01:00
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// Config memory
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} else if ((vaddr >= CONFIG_MEMORY_VADDR) && (vaddr < CONFIG_MEMORY_VADDR_END)) {
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ConfigMem::Read<T>(var, vaddr);
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2015-01-02 05:41:34 +00:00
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// Shared page
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} else if ((vaddr >= SHARED_PAGE_VADDR) && (vaddr < SHARED_PAGE_VADDR_END)) {
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SharedPage::Read<T>(var, vaddr);
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2014-12-30 03:35:06 +00:00
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// DSP memory
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2015-05-09 04:39:56 +01:00
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} else if ((vaddr >= DSP_RAM_VADDR) && (vaddr < DSP_RAM_VADDR_END)) {
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var = *((const T*)&g_dsp_mem[vaddr - DSP_RAM_VADDR]);
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2014-12-30 03:35:06 +00:00
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2014-04-26 06:27:25 +01:00
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// VRAM
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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var = *((const T*)&g_vram[vaddr - VRAM_VADDR]);
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2014-04-26 06:27:25 +01:00
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2014-04-04 03:04:50 +01:00
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} else {
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2014-12-06 01:53:49 +00:00
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LOG_ERROR(HW_Memory, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, vaddr);
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2014-04-01 23:18:02 +01:00
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}
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2013-09-19 04:52:51 +01:00
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}
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template <typename T>
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2014-08-28 19:20:55 +01:00
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inline void Write(const VAddr vaddr, const T data) {
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2014-08-03 00:46:47 +01:00
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2014-05-08 02:04:55 +01:00
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// Kernel memory command buffer
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2015-05-09 04:39:56 +01:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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*(T*)&g_tls_mem[vaddr - TLS_AREA_VADDR] = data;
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2014-04-13 02:55:36 +01:00
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2014-04-30 04:16:12 +01:00
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// ExeFS:/.code is loaded here
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2015-05-09 04:39:56 +01:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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*(T*)&g_exefs_code[vaddr - PROCESS_IMAGE_VADDR] = data;
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2014-04-30 04:16:12 +01:00
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2014-11-23 03:35:45 +00:00
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// FCRAM - linear heap
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2015-05-09 04:39:56 +01:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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*(T*)&g_heap_linear[vaddr - LINEAR_HEAP_VADDR] = data;
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2014-04-18 02:05:34 +01:00
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// FCRAM - application heap
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2014-04-25 04:56:06 +01:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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*(T*)&g_heap[vaddr - HEAP_VADDR] = data;
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2014-04-04 03:04:50 +01:00
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2014-04-25 04:56:06 +01:00
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// Shared memory
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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*(T*)&g_shared_mem[vaddr - SHARED_MEMORY_VADDR] = data;
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2014-04-25 04:56:06 +01:00
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2014-04-26 06:27:25 +01:00
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// VRAM
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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*(T*)&g_vram[vaddr - VRAM_VADDR] = data;
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2014-04-26 06:27:25 +01:00
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2014-12-30 03:35:06 +00:00
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// DSP memory
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2015-05-09 04:39:56 +01:00
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} else if ((vaddr >= DSP_RAM_VADDR) && (vaddr < DSP_RAM_VADDR_END)) {
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*(T*)&g_dsp_mem[vaddr - DSP_RAM_VADDR] = data;
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2014-12-30 03:35:06 +00:00
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2014-05-07 04:32:04 +01:00
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//} else if ((vaddr & 0xFFFF0000) == 0x1FF80000) {
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2015-01-21 01:16:47 +00:00
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// ASSERT_MSG(MEMMAP, false, "umimplemented write to Configuration Memory");
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2014-05-07 04:32:04 +01:00
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//} else if ((vaddr & 0xFFFFF000) == 0x1FF81000) {
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2015-01-21 01:16:47 +00:00
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// ASSERT_MSG(MEMMAP, false, "umimplemented write to shared page");
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2014-08-03 00:46:47 +01:00
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2014-04-04 03:04:50 +01:00
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// Error out...
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2014-04-01 23:18:02 +01:00
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} else {
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2014-12-06 01:53:49 +00:00
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LOG_ERROR(HW_Memory, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, vaddr);
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2014-04-01 23:18:02 +01:00
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}
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2013-09-19 04:52:51 +01:00
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}
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2014-08-28 19:20:55 +01:00
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u8 *GetPointer(const VAddr vaddr) {
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2014-05-08 02:04:55 +01:00
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// Kernel memory command buffer
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2015-05-09 04:39:56 +01:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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return g_tls_mem + (vaddr - TLS_AREA_VADDR);
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2014-05-08 02:04:55 +01:00
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2014-04-30 04:16:12 +01:00
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// ExeFS:/.code is loaded here
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2015-05-09 04:39:56 +01:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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return g_exefs_code + (vaddr - PROCESS_IMAGE_VADDR);
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2014-04-30 04:16:12 +01:00
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2014-11-23 03:35:45 +00:00
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// FCRAM - linear heap
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2015-05-09 04:39:56 +01:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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return g_heap_linear + (vaddr - LINEAR_HEAP_VADDR);
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2014-04-18 02:15:40 +01:00
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2014-04-18 02:05:34 +01:00
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// FCRAM - application heap
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2014-04-18 02:40:42 +01:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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return g_heap + (vaddr - HEAP_VADDR);
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2014-04-17 23:40:42 +01:00
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2014-04-25 04:56:06 +01:00
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// Shared memory
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2014-05-15 23:56:28 +01:00
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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return g_shared_mem + (vaddr - SHARED_MEMORY_VADDR);
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2014-04-25 04:56:06 +01:00
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2014-04-26 06:27:25 +01:00
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// VRAM
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2014-07-23 03:38:21 +01:00
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-03 06:13:29 +00:00
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return g_vram + (vaddr - VRAM_VADDR);
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2014-04-26 06:27:25 +01:00
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2014-04-07 03:56:08 +01:00
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} else {
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2014-12-06 01:53:49 +00:00
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LOG_ERROR(HW_Memory, "unknown GetPointer @ 0x%08x", vaddr);
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2014-04-01 23:18:02 +01:00
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return 0;
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}
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2014-03-25 14:50:34 +00:00
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}
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2015-05-13 02:38:29 +01:00
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u8* GetPhysicalPointer(PAddr address) {
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return GetPointer(PhysicalToVirtualAddress(address));
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2015-04-28 02:59:06 +01:00
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}
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2014-08-28 19:20:55 +01:00
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u8 Read8(const VAddr addr) {
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2014-07-25 00:46:10 +01:00
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u8 data = 0;
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Read<u8>(data, addr);
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2014-08-28 19:20:55 +01:00
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return data;
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2013-09-19 04:52:51 +01:00
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}
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2014-08-28 19:20:55 +01:00
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u16 Read16(const VAddr addr) {
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2014-07-25 00:46:10 +01:00
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u16_le data = 0;
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Read<u16_le>(data, addr);
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2015-05-12 22:17:04 +01:00
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return data;
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2013-09-19 04:52:51 +01:00
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}
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2014-08-28 19:20:55 +01:00
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u32 Read32(const VAddr addr) {
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2014-07-25 00:46:10 +01:00
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u32_le data = 0;
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Read<u32_le>(data, addr);
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2015-05-12 22:17:04 +01:00
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return data;
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2013-09-19 04:52:51 +01:00
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}
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2015-03-11 20:10:14 +00:00
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u64 Read64(const VAddr addr) {
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u64_le data = 0;
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Read<u64_le>(data, addr);
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2015-05-12 22:17:04 +01:00
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return data;
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2013-09-19 04:52:51 +01:00
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}
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2014-08-28 19:20:55 +01:00
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void Write8(const VAddr addr, const u8 data) {
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2014-07-05 04:46:16 +01:00
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Write<u8>(addr, data);
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2013-09-19 04:52:51 +01:00
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}
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2014-08-28 19:20:55 +01:00
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void Write16(const VAddr addr, const u16 data) {
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2014-07-05 04:46:16 +01:00
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Write<u16_le>(addr, data);
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2013-09-19 04:52:51 +01:00
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}
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2014-08-28 19:20:55 +01:00
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void Write32(const VAddr addr, const u32 data) {
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2014-07-05 04:46:16 +01:00
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Write<u32_le>(addr, data);
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2013-09-19 04:52:51 +01:00
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}
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2014-08-28 19:20:55 +01:00
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void Write64(const VAddr addr, const u64 data) {
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2014-07-05 04:46:16 +01:00
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Write<u64_le>(addr, data);
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2013-09-19 04:52:51 +01:00
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}
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2014-08-28 19:20:55 +01:00
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void WriteBlock(const VAddr addr, const u8* data, const size_t size) {
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2014-09-28 16:30:29 +01:00
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u32 offset = 0;
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2014-08-17 19:23:54 +01:00
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while (offset < (size & ~3)) {
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Write32(addr + offset, *(u32*)&data[offset]);
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offset += 4;
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}
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2014-06-24 23:51:31 +01:00
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2014-08-17 19:23:54 +01:00
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if (size & 2) {
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Write16(addr + offset, *(u16*)&data[offset]);
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offset += 2;
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}
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2014-06-24 23:51:31 +01:00
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if (size & 1)
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Write8(addr + offset, data[offset]);
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}
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2013-09-19 04:52:51 +01:00
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} // namespace
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