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Fixup: Xn|SP are 64 bit addresses encoded in the Rn field

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James Rowe 2018-01-23 22:16:07 -07:00 committed by MerryMage
parent ae880d8391
commit 589ad7232f
1 changed files with 6 additions and 6 deletions
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12
src/frontend/A64/translate/impl/load_store_register_unprivileged.cpp
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@ -17,9 +17,9 @@ static bool StoreRegister(TranslatorVisitor& tv, IREmitter& ir, const size_t dat
if (Rn == Reg::SP) { if (Rn == Reg::SP) {
// TODO: Check Stack Alignment // TODO: Check Stack Alignment
address = tv.SP(datasize); address = tv.SP(64);
} else { } else {
address = tv.X(datasize, Rn); address = tv.X(64, Rn);
} }
address = ir.Add(address, ir.Imm64(offset)); address = ir.Add(address, ir.Imm64(offset));
IR::UAny data = tv.X(datasize, Rt); IR::UAny data = tv.X(datasize, Rt);
@ -35,9 +35,9 @@ static bool LoadRegister(TranslatorVisitor& tv, IREmitter& ir, const size_t data
if (Rn == Reg::SP) { if (Rn == Reg::SP) {
// TODO: Check Stack Alignment // TODO: Check Stack Alignment
address = tv.SP(datasize); address = tv.SP(64);
} else { } else {
address = tv.X(datasize, Rn); address = tv.X(64, Rn);
} }
address = ir.Add(address, ir.Imm64(offset)); address = ir.Add(address, ir.Imm64(offset));
IR::UAny data = tv.Mem(address, datasize / 8, acctype); IR::UAny data = tv.Mem(address, datasize / 8, acctype);
@ -69,9 +69,9 @@ static bool LoadRegisterSigned(TranslatorVisitor& tv, IREmitter& ir, const size_
IR::U64 address; IR::U64 address;
if (Rn == Reg::SP) { if (Rn == Reg::SP) {
// TODO: Check Stack Alignment // TODO: Check Stack Alignment
address = tv.SP(datasize); address = tv.SP(64);
} else { } else {
address = tv.X(datasize, Rn); address = tv.X(64, Rn);
} }
address = ir.Add(address, ir.Imm64(offset)); address = ir.Add(address, ir.Imm64(offset));