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simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)

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This commit is contained in:
MerryMage 2018-02-13 19:01:47 +00:00
parent 8cebb87d0d
commit ccf7df057b
1 changed files with 8 additions and 2 deletions
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10
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -27,7 +27,10 @@ bool TranslatorVisitor::CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd)
const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm); const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorGreaterEqualSigned(esize, operand1, operand2); IR::U128 result = ir.VectorGreaterEqualSigned(esize, operand1, operand2);
if (datasize == 64) {
result = ir.VectorZeroUpper(result);
}
V(datasize, Vd, result); V(datasize, Vd, result);
return true; return true;
} }
@ -188,7 +191,10 @@ bool TranslatorVisitor::CMHS_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm); const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorGreaterEqualUnsigned(esize, operand1, operand2); IR::U128 result = ir.VectorGreaterEqualUnsigned(esize, operand1, operand2);
if (datasize == 64) {
result = ir.VectorZeroUpper(result);
}
V(datasize, Vd, result); V(datasize, Vd, result);
return true; return true;
} }