MerryMage
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856298577d
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EmitX64: Don't give MOVSX or MOVZX an immediate oparg
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2016-08-06 01:03:39 +01:00 |
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MerryMage
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640ce48baa
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VFP: Implement {Get,Set}ExtendedRegister{32,64}
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2016-08-05 19:06:10 +01:00 |
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MerryMage
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4c0a85f3b3
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EmitX64: Correct EmitPack2x32To1x64 implementation
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2016-08-05 18:43:24 +01:00 |
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MerryMage
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d80dcc5367
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BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64
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2016-08-05 15:27:29 +01:00 |
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MerryMage
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b4aa01ccf4
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Merge remote-tracking branch 'tilkax/master'
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2016-08-05 14:14:06 +01:00 |
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MerryMage
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94e75ad32f
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BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg}
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2016-08-05 14:11:27 +01:00 |
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MerryMage
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ca40015145
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IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
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2016-08-05 14:07:27 +01:00 |
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Tillmann Karras
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72c503016c
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Fix Pack2x32To1x64
Not sure how to fix this properly.
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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3fdc093d10
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Add more IR opcodes for multiply instructions
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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af27ef8d6c
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Optionally disassemble x86_64 code using LLVM
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2016-08-05 02:08:41 +01:00 |
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Tillmann Karras
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2488926341
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Add IR opcode RotateRightExtended
to rotate through the carry flag
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2016-08-03 00:47:16 +01:00 |
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MerryMage
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4414ec5bc8
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RegAlloc: Allow allocation of XMM registers
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2016-08-02 13:46:12 +01:00 |
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MerryMage
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864081d1a0
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BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR
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2016-08-02 12:00:11 +01:00 |
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MerryMage
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93af160c97
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arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface
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2016-08-02 11:54:02 +01:00 |
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MerryMage
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be87038ffd
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IROpt: Port get/set elimination pass to current IR
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2016-08-02 11:51:05 +01:00 |
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MerryMage
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51448aa06d
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More Speed
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2016-07-22 23:55:00 +01:00 |
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MerryMage
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5fbfc6c155
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Implement some simple IR optimizations (get/set eliminiation and DCE)
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2016-07-21 21:48:45 +01:00 |
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MerryMage
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90d317b868
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Implement memory endianness. Implement Thumb SETEND instruction.
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2016-07-20 15:34:17 +01:00 |
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MerryMage
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3f11a149d7
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Implement Thumb Instructions: BLX (imm), BL (imm)
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2016-07-18 22:18:58 +01:00 |
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MerryMage
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e0d6e28b67
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Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
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2016-07-18 21:04:39 +01:00 |
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MerryMage
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8a310777a1
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backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC
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2016-07-18 20:01:48 +01:00 |
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Subv
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703a46ec99
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Pass the current IR::Block by reference to the emitter.
This avoids calling the copy constructor more times than needed.
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2016-07-18 11:27:33 -05:00 |
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MerryMage
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3720da4e19
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Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
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2016-07-16 19:23:42 +01:00 |
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MerryMage
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9b2aff166a
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Implement arm_SVC
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2016-07-14 14:29:46 +01:00 |
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MerryMage
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7d7751c157
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Allow IR blocks to require a cond for block entry.
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
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2016-07-14 12:52:53 +01:00 |
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MerryMage
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4ab4ca58f9
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backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight
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2016-07-14 09:02:27 +01:00 |
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MerryMage
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08e848044d
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backend_x64: Inline Routines::GenReturnFromRunCode into emitted code
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2016-07-12 16:46:27 +01:00 |
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MerryMage
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8449deb0bc
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MSVC support
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2016-07-12 13:28:09 +01:00 |
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MerryMage
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09420d190b
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IR: Implement IR microinstructions ALUWritePC and LoadWritePC
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2016-07-12 10:58:14 +01:00 |
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MerryMage
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1410221b47
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Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
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2016-07-11 23:11:05 +01:00 |
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MerryMage
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e7922e4fef
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Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
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2016-07-11 22:43:53 +01:00 |
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MerryMage
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d11df9067d
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Implement thumb1_BIC_reg
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2016-07-10 10:44:45 +08:00 |
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MerryMage
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98a64a92b1
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Implement thumb1_ORR_reg
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2016-07-10 09:06:38 +08:00 |
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MerryMage
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8145b33882
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Implemented thumb1_ROR_reg
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2016-07-10 08:18:17 +08:00 |
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MerryMage
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aa72323823
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Implement thumb1_CMP_imm
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2016-07-08 21:32:01 +08:00 |
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MerryMage
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92142d5a22
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Implement thumb1_SUB_reg
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2016-07-08 18:49:30 +08:00 |
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MerryMage
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df0c324923
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Implement thumb1_EOR_reg
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2016-07-08 18:14:54 +08:00 |
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MerryMage
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8a0511d297
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Implement thumb1_AND_reg
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2016-07-08 17:44:53 +08:00 |
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MerryMage
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d0b48bfb59
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Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
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2016-07-08 17:44:51 +08:00 |
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MerryMage
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e93fb0ba2b
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EmitX64: remove emit_fns map, use a switch statement instead
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2016-07-08 15:28:56 +08:00 |
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MerryMage
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421ab344ad
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EmitX64::EmitTerminalInterpret: Restore RSP before CALL
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2016-07-07 22:03:45 +08:00 |
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MerryMage
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e5f6450a24
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Start implementing Thumb disassembler
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2016-07-07 21:51:47 +08:00 |
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MerryMage
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f31b530703
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Fuzz thumb instructions
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2016-07-07 19:01:47 +08:00 |
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MerryMage
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5711e62419
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Implement terminal instructions
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2016-07-07 17:53:09 +08:00 |
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MerryMage
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14388ea690
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Proper implementation of Arm::Translate
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2016-07-04 21:37:50 +08:00 |
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MerryMage
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d743adf518
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Reorganisation, Import Skyeye, This is a mess
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2016-07-04 17:22:11 +08:00 |
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MerryMage
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65df15633d
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First Commit
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2016-07-01 21:01:06 +08:00 |
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