Encode imm, needs further testing

src/instructions.rs

@@ -242,6 +242,14 @@ pub fn instruction(op: &str) -> (Kind, Vec<Value>) {
             Kind::Pseudo(Pseudo {}),
             vec![Value::Register, Value::Immediate],
         ),
+        "lui" => (
+            Kind::U(U {
+                imm: to_bits(0),
+                rd: to_bits(0),
+                opcode: to_bits(0b0110111),
+            }),
+            vec![Value::Register, Value::Immediate],
+        ),
 
         // Memory
 

src/main.rs

@@ -62,19 +62,33 @@ fn main() -> anyhow::Result<()> {
             ]
         )
         .0 // 011001101010000001010010110000000
-        // Ripes: 011001101010000001010010110000000
+           // Ripes: 011001101010000001010010110000000
     );
     println!(
         "addi a0 a0 1: {}",
-        with_imm(with_reg_args(
+        with_imm(
-            instruction("addi"),
+            with_reg_args(
-            vec![
+                instruction("addi"),
-                env.alias_to_register("a0").unwrap() as u32,
+                vec![
-                env.alias_to_register("a0").unwrap() as u32
+                    env.alias_to_register("a0").unwrap(),
-            ]
+                    env.alias_to_register("a0").unwrap()
-        ), 1)
+                ]
+            ),
+            1
+        )
         .0 // 00000000000101010000010100010011
-        // Ripes: 00000000000101010000010100010011
+           // Ripes: 00000000000101010000010100010011
+    );
+    println!(
+        "lui a0 1:     {}",
+        with_imm(
+            with_reg_args(
+                instruction("lui"),
+                vec![env.alias_to_register("a0").unwrap()]
+            ),
+            1
+        )
+        .0
     );
 
     Ok(())