2016-09-02 17:34:33 +01:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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#include "common/bit_util.h"
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#include "common/common_types.h"
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2018-01-26 13:51:48 +00:00
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namespace Dynarmic::A32 {
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2016-09-02 17:34:33 +01:00
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/**
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* Program Status Register
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*
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* | Bit(s) | Description |
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* |:-------:|:----------------------------------------------|
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* | N | Negative |
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* | Z | Zero |
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* | C | Carry |
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* | V | Overflow |
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* | Q | Sticky overflow for DSP-oriented instructions |
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* | IT[1:0] | Lower two bits of the If-Then execution state |
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* | J | Jazelle bit |
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* | GE | Greater-than or Equal |
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* | IT[7:2] | Upper six bits of the If-Then execution state |
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* | E | Endian (0 is little endian, 1 is big endian) |
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* | A | Imprecise data abort (disables them when set) |
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* | I | IRQ interrupts (disabled when set) |
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* | F | FIQ interrupts (disabled when set) |
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* | T | Thumb bit |
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* | M | Current processor mode |
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*/
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class PSR final {
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public:
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/// Valid processor modes that may be indicated.
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enum class Mode : u32
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{
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User = 0b10000,
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FIQ = 0b10001,
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IRQ = 0b10010,
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Supervisor = 0b10011,
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Monitor = 0b10110,
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Abort = 0b10111,
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Hypervisor = 0b11010,
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Undefined = 0b11011,
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System = 0b11111
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};
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/// Instruction sets that may be signified through a PSR.
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enum class InstructionSet
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{
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ARM,
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Jazelle,
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Thumb,
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ThumbEE
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};
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PSR() = default;
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explicit PSR(u32 data) : value{data & mask} {}
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PSR& operator=(u32 data) {
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value = data & mask;
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return *this;
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}
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bool N() const {
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return Common::Bit<31>(value);
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}
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void N(bool set) {
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value = (value & ~0x80000000) | static_cast<u32>(set) << 31;
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}
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bool Z() const {
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return Common::Bit<30>(value);
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}
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void Z(bool set) {
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value = (value & ~0x40000000) | static_cast<u32>(set) << 30;
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}
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bool C() const {
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return Common::Bit<29>(value);
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}
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void C(bool set) {
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value = (value & ~0x20000000) | static_cast<u32>(set) << 29;
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}
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bool V() const {
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return Common::Bit<28>(value);
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}
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void V(bool set) {
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value = (value & ~0x10000000) | static_cast<u32>(set) << 28;
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}
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bool Q() const {
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return Common::Bit<27>(value);
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}
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void Q(bool set) {
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value = (value & ~0x8000000) | static_cast<u32>(set) << 27;
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}
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bool J() const {
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return Common::Bit<24>(value);
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}
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void J(bool set) {
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value = (value & ~0x1000000) | static_cast<u32>(set) << 24;
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}
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u32 GE() const {
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return Common::Bits<16, 19>(value);
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}
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void GE(u32 data) {
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value = (value & ~0xF0000) | (data & 0xF) << 16;
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}
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u32 IT() const {
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return (value & 0x6000000) >> 25 | (value & 0xFC00) >> 8;
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}
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void IT(u32 data) {
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value = (value & ~0x000FC00) | (data & 0b11111100) << 8;
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value = (value & ~0x6000000) | (data & 0b00000011) << 25;
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}
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bool E() const {
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return Common::Bit<9>(value);
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}
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void E(bool set) {
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value = (value & ~0x200) | static_cast<u32>(set) << 9;
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}
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bool A() const {
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return Common::Bit<8>(value);
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}
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void A(bool set) {
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value = (value & ~0x100) | static_cast<u32>(set) << 8;
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}
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bool I() const {
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return Common::Bit<7>(value);
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}
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void I(bool set) {
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value = (value & ~0x80) | static_cast<u32>(set) << 7;
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}
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bool F() const {
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return Common::Bit<6>(value);
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}
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void F(bool set) {
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value = (value & ~0x40) | static_cast<u32>(set) << 6;
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}
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bool T() const {
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return Common::Bit<5>(value);
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}
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void T(bool set) {
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value = (value & ~0x20) | static_cast<u32>(set) << 5;
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}
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Mode M() const {
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return static_cast<Mode>(Common::Bits<0, 4>(value));
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}
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void M(Mode mode) {
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value = (value & ~0x1F) | (static_cast<u32>(mode) & 0x1F);
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}
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u32 Value() const {
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return value;
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}
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InstructionSet CurrentInstructionSet() const {
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const bool j_bit = J();
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const bool t_bit = T();
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if (j_bit && t_bit)
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return InstructionSet::ThumbEE;
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if (t_bit)
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return InstructionSet::Thumb;
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if (j_bit)
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return InstructionSet::Jazelle;
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return InstructionSet::ARM;
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}
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void CurrentInstructionSet(InstructionSet instruction_set) {
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switch (instruction_set) {
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case InstructionSet::ARM:
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T(false);
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J(false);
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break;
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case InstructionSet::Jazelle:
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T(false);
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J(true);
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break;
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case InstructionSet::Thumb:
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T(true);
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J(false);
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break;
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case InstructionSet::ThumbEE:
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T(true);
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J(true);
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break;
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}
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}
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private:
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// Bits 20-23 are reserved and should be zero.
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static constexpr u32 mask = 0xFF0FFFFF;
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u32 value = 0;
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};
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inline bool operator==(PSR lhs, PSR rhs) {
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return lhs.Value() == rhs.Value();
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}
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inline bool operator!=(PSR lhs, PSR rhs) {
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return !operator==(lhs, rhs);
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}
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2018-01-26 13:51:48 +00:00
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} // namespace Dynarmic::A32
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