2018-01-01 22:34:05 +00:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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#include <boost/optional.hpp>
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2018-01-04 21:12:02 +00:00
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#include "backend_x64/a32_jitstate.h"
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2018-01-23 19:16:39 +00:00
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#include "backend_x64/block_range_information.h"
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2018-01-01 22:34:05 +00:00
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#include "backend_x64/emit_x64.h"
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2018-01-04 21:12:02 +00:00
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#include "dynarmic/A32/a32.h"
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2018-01-27 22:36:55 +00:00
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#include "dynarmic/A32/config.h"
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2018-01-01 22:34:05 +00:00
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#include "frontend/A32/location_descriptor.h"
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#include "frontend/ir/terminal.h"
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2018-01-26 13:51:48 +00:00
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namespace Dynarmic::BackendX64 {
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2018-01-01 22:34:05 +00:00
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2018-01-01 23:40:34 +00:00
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class RegAlloc;
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struct A32EmitContext final : public EmitContext {
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A32EmitContext(RegAlloc& reg_alloc, IR::Block& block);
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A32::LocationDescriptor Location() const;
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bool FPSCR_RoundTowardsZero() const override;
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bool FPSCR_FTZ() const override;
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bool FPSCR_DN() const override;
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};
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2018-01-23 19:16:39 +00:00
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class A32EmitX64 final : public EmitX64 {
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2018-01-01 22:34:05 +00:00
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public:
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2018-02-03 14:28:57 +00:00
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A32EmitX64(BlockOfCode& code, A32::UserConfig config, A32::Jit* jit_interface);
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2018-01-27 02:25:27 +00:00
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~A32EmitX64() override;
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2018-01-01 22:34:05 +00:00
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/**
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* Emit host machine code for a basic block with intermediate representation `ir`.
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* @note ir is modified.
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*/
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BlockDescriptor Emit(IR::Block& ir);
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2018-01-23 19:16:39 +00:00
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void ClearCache() override;
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void InvalidateCacheRanges(const boost::icl::interval_set<u32>& ranges);
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2018-01-01 22:34:05 +00:00
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protected:
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2018-01-27 22:36:55 +00:00
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const A32::UserConfig config;
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2018-01-04 21:12:02 +00:00
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A32::Jit* jit_interface;
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2018-01-23 19:16:39 +00:00
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BlockRangeInformation<u32> block_ranges;
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2018-01-04 21:12:02 +00:00
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const void* read_memory_8;
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const void* read_memory_16;
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const void* read_memory_32;
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const void* read_memory_64;
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const void* write_memory_8;
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const void* write_memory_16;
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const void* write_memory_32;
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const void* write_memory_64;
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void GenMemoryAccessors();
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2018-01-01 22:34:05 +00:00
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// Microinstruction emitters
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#define OPCODE(...)
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2018-01-01 23:40:34 +00:00
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#define A32OPC(name, type, ...) void EmitA32##name(A32EmitContext& ctx, IR::Inst* inst);
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2018-01-07 00:11:57 +00:00
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#define A64OPC(...)
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2018-01-01 22:34:05 +00:00
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#include "frontend/ir/opcodes.inc"
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#undef OPCODE
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#undef A32OPC
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2018-01-07 00:11:57 +00:00
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#undef A64OPC
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2018-01-01 22:34:05 +00:00
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// Terminal instruction emitters
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void EmitTerminalImpl(IR::Term::Interpret terminal, IR::LocationDescriptor initial_location) override;
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void EmitTerminalImpl(IR::Term::ReturnToDispatch terminal, IR::LocationDescriptor initial_location) override;
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void EmitTerminalImpl(IR::Term::LinkBlock terminal, IR::LocationDescriptor initial_location) override;
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void EmitTerminalImpl(IR::Term::LinkBlockFast terminal, IR::LocationDescriptor initial_location) override;
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void EmitTerminalImpl(IR::Term::PopRSBHint terminal, IR::LocationDescriptor initial_location) override;
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void EmitTerminalImpl(IR::Term::If terminal, IR::LocationDescriptor initial_location) override;
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2018-01-07 16:33:02 +00:00
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void EmitTerminalImpl(IR::Term::CheckBit terminal, IR::LocationDescriptor initial_location) override;
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2018-01-01 22:34:05 +00:00
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void EmitTerminalImpl(IR::Term::CheckHalt terminal, IR::LocationDescriptor initial_location) override;
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// Patching
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void EmitPatchJg(const IR::LocationDescriptor& target_desc, CodePtr target_code_ptr = nullptr) override;
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void EmitPatchJmp(const IR::LocationDescriptor& target_desc, CodePtr target_code_ptr = nullptr) override;
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void EmitPatchMovRcx(CodePtr target_code_ptr = nullptr) override;
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};
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2018-01-26 13:51:48 +00:00
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} // namespace Dynarmic::BackendX64
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