2022-12-29 17:01:17 +00:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2022 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include <vector>
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2022-12-31 16:26:55 +00:00
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#include <catch2/catch_test_macros.hpp>
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2022-12-29 17:01:17 +00:00
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#include <mcl/stdint.hpp>
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#include "./testenv.h"
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using namespace Dynarmic;
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namespace {
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struct TestCase {
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u32 a;
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u32 b;
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u32 fmax;
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u32 fmaxnm;
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u32 fmin;
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u32 fminnm;
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};
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const std::vector test_cases{
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// a b fmax fmaxnm fmin fminnm
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TestCase{0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, // +0.0
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TestCase{0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, // -0.0
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TestCase{0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000}, // +1.0
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TestCase{0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000}, // -1.0
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TestCase{0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000}, // +Inf
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TestCase{0xff800000, 0xff800000, 0xff800000, 0xff800000, 0xff800000, 0xff800000}, // -Inf
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TestCase{0x7fc00041, 0x7fc00041, 0x7fc00041, 0x7fc00041, 0x7fc00041, 0x7fc00041}, // QNaN
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TestCase{0x7f800042, 0x7f800042, 0x7fc00042, 0x7fc00042, 0x7fc00042, 0x7fc00042}, // SNaN
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TestCase{0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x80000000, 0x80000000}, // (+0.0, -0.0)
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TestCase{0x3f800000, 0xbf800000, 0x3f800000, 0x3f800000, 0xbf800000, 0xbf800000}, // (+1.0, -1.0)
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TestCase{0x3f800000, 0x7f800000, 0x7f800000, 0x7f800000, 0x3f800000, 0x3f800000}, // (+1.0, +Inf)
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TestCase{0x3f800000, 0xff800000, 0x3f800000, 0x3f800000, 0xff800000, 0xff800000}, // (+1.0, -Inf)
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TestCase{0x7f800000, 0xff800000, 0x7f800000, 0x7f800000, 0xff800000, 0xff800000}, // (+Inf, -Inf)
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TestCase{0x3f800000, 0x7fc00041, 0x7fc00041, 0x3f800000, 0x7fc00041, 0x3f800000}, // (+1.0, QNaN)
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TestCase{0x3f800000, 0x7f800042, 0x7fc00042, 0x7fc00042, 0x7fc00042, 0x7fc00042}, // (+1.0, SNaN)
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TestCase{0x7f800000, 0x7fc00041, 0x7fc00041, 0x7f800000, 0x7fc00041, 0x7f800000}, // (+Inf, QNaN)
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TestCase{0x7f800000, 0x7f800042, 0x7fc00042, 0x7fc00042, 0x7fc00042, 0x7fc00042}, // (+Inf, SNaN)
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TestCase{0x7fc00041, 0x7f800042, 0x7fc00042, 0x7fc00042, 0x7fc00042, 0x7fc00042}, // (QNaN, SNaN)
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TestCase{0xffa57454, 0xe343a6b3, 0xffe57454, 0xffe57454, 0xffe57454, 0xffe57454},
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};
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const std::vector unidirectional_test_cases{
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TestCase{0x7fc00041, 0x7fc00043, 0x7fc00041, 0x7fc00041, 0x7fc00041, 0x7fc00041}, // (QNaN, QNaN)
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TestCase{0x7f800042, 0x7f800044, 0x7fc00042, 0x7fc00042, 0x7fc00042, 0x7fc00042}, // (SNaN, SNaN)
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};
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constexpr u32 default_nan = 0x7fc00000;
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bool is_nan(u32 value) {
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return (value & 0x7f800000) == 0x7f800000 && (value & 0x007fffff) != 0;
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}
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u32 force_default_nan(u32 value) {
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return is_nan(value) ? default_nan : value;
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}
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template<typename Fn>
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void run_test(u32 instruction, Fn fn) {
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A64TestEnv env;
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A64::Jit jit{A64::UserConfig{&env}};
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env.code_mem.emplace_back(instruction); // FMAX S0, S1, S2
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env.code_mem.emplace_back(0x14000000); // B .
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for (const auto base_fpcr : {0, 0x01000000}) {
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for (const auto test_case : test_cases) {
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INFO(test_case.a);
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INFO(test_case.b);
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jit.SetFpcr(base_fpcr);
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jit.SetVector(0, {42, 0});
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jit.SetVector(1, {test_case.a, 0});
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jit.SetVector(2, {test_case.b, 0});
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetVector(0)[0] == fn(test_case));
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jit.SetVector(0, {42, 0});
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jit.SetVector(1, {test_case.b, 0});
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jit.SetVector(2, {test_case.a, 0});
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetVector(0)[0] == fn(test_case));
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jit.SetFpcr(base_fpcr | 0x02000000);
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jit.SetVector(0, {42, 0});
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jit.SetVector(1, {test_case.a, 0});
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jit.SetVector(2, {test_case.b, 0});
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetVector(0)[0] == force_default_nan(fn(test_case)));
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jit.SetVector(0, {42, 0});
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jit.SetVector(1, {test_case.b, 0});
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jit.SetVector(2, {test_case.a, 0});
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetVector(0)[0] == force_default_nan(fn(test_case)));
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}
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for (const auto test_case : unidirectional_test_cases) {
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INFO(test_case.a);
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INFO(test_case.b);
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jit.SetFpcr(base_fpcr);
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jit.SetVector(0, {42, 0});
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jit.SetVector(1, {test_case.a, 0});
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jit.SetVector(2, {test_case.b, 0});
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetVector(0)[0] == fn(test_case));
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jit.SetFpcr(base_fpcr | 0x02000000);
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jit.SetVector(0, {42, 0});
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jit.SetVector(1, {test_case.a, 0});
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jit.SetVector(2, {test_case.b, 0});
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetVector(0)[0] == force_default_nan(fn(test_case)));
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}
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}
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}
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} // namespace
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TEST_CASE("A64: FMAX (scalar)", "[a64]") {
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run_test(0x1e224820, [](const TestCase& test_case) { return test_case.fmax; });
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}
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TEST_CASE("A64: FMIN (scalar)", "[a64]") {
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run_test(0x1e225820, [](const TestCase& test_case) { return test_case.fmin; });
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}
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TEST_CASE("A64: FMAXNM (scalar)", "[a64]") {
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run_test(0x1e226820, [](const TestCase& test_case) { return test_case.fmaxnm; });
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}
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TEST_CASE("A64: FMINNM (scalar)", "[a64]") {
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run_test(0x1e227820, [](const TestCase& test_case) { return test_case.fminnm; });
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}
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TEST_CASE("A64: FMAX (vector)", "[a64]") {
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run_test(0x4e22f420, [](const TestCase& test_case) { return test_case.fmax; });
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}
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TEST_CASE("A64: FMIN (vector)", "[a64]") {
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run_test(0x4ea2f420, [](const TestCase& test_case) { return test_case.fmin; });
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}
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TEST_CASE("A64: FMAXNM (vector)", "[a64]") {
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run_test(0x4e22c420, [](const TestCase& test_case) { return test_case.fmaxnm; });
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}
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TEST_CASE("A64: FMINNM (vector)", "[a64]") {
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run_test(0x4ea2c420, [](const TestCase& test_case) { return test_case.fminnm; });
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}
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