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IR: Implement FPVectorNeg

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This commit is contained in:
MerryMage 2018-07-25 13:25:35 +01:00
parent 934132e0c5
commit 04f325a05e
4 changed files with 50 additions and 0 deletions
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33
src/backend_x64/emit_x64_vector_floating_point.cpp
View file

@ -555,6 +555,39 @@ void EmitX64::EmitFPVectorMulAdd64(EmitContext& ctx, IR::Inst* inst) {
EmitFPVectorMulAdd<64>(code, ctx, inst); EmitFPVectorMulAdd<64>(code, ctx, inst);
} }
void EmitX64::EmitFPVectorNeg16(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
const Xbyak::Address mask = code.MConst(xword, 0x8000800080008000, 0x8000800080008000);
code.pxor(a, mask);
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitFPVectorNeg32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
const Xbyak::Address mask = code.MConst(xword, 0x8000000080000000, 0x8000000080000000);
code.pxor(a, mask);
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitFPVectorNeg64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
const Xbyak::Address mask = code.MConst(xword, 0x8000000000000000, 0x8000000000000000);
code.pxor(a, mask);
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitFPVectorPairedAdd32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPVectorPairedAdd32(EmitContext& ctx, IR::Inst* inst) {
EmitThreeOpVectorOperation<32, PairedIndexer>(code, ctx, inst, &Xbyak::CodeGenerator::haddps); EmitThreeOpVectorOperation<32, PairedIndexer>(code, ctx, inst, &Xbyak::CodeGenerator::haddps);
} }

13
src/frontend/ir/ir_emitter.cpp
View file

@ -1707,6 +1707,19 @@ U128 IREmitter::FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const
return {}; return {};
} }
U128 IREmitter::FPVectorNeg(size_t esize, const U128& a) {
switch (esize) {
case 16:
return Inst<U128>(Opcode::FPVectorNeg16, a);
case 32:
return Inst<U128>(Opcode::FPVectorNeg32, a);
case 64:
return Inst<U128>(Opcode::FPVectorNeg64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorPairedAdd(size_t esize, const U128& a, const U128& b) { U128 IREmitter::FPVectorPairedAdd(size_t esize, const U128& a, const U128& b) {
switch (esize) { switch (esize) {
case 32: case 32:

1
src/frontend/ir/ir_emitter.h
View file

@ -301,6 +301,7 @@ public:
U128 FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b); U128 FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b);
U128 FPVectorMul(size_t esize, const U128& a, const U128& b); U128 FPVectorMul(size_t esize, const U128& a, const U128& b);
U128 FPVectorMulAdd(size_t esize, const U128& addend, const U128& op1, const U128& op2); U128 FPVectorMulAdd(size_t esize, const U128& addend, const U128& op1, const U128& op2);
U128 FPVectorNeg(size_t esize, const U128& a);
U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b); U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b);
U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b); U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a); U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);

3
src/frontend/ir/opcodes.inc
View file

@ -443,6 +443,9 @@ OPCODE(FPVectorMul32, T::U128, T::U128,
OPCODE(FPVectorMul64, T::U128, T::U128, T::U128 ) OPCODE(FPVectorMul64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorMulAdd32, T::U128, T::U128, T::U128, T::U128 ) OPCODE(FPVectorMulAdd32, T::U128, T::U128, T::U128, T::U128 )
OPCODE(FPVectorMulAdd64, T::U128, T::U128, T::U128, T::U128 ) OPCODE(FPVectorMulAdd64, T::U128, T::U128, T::U128, T::U128 )
OPCODE(FPVectorNeg16, T::U128, T::U128 )
OPCODE(FPVectorNeg32, T::U128, T::U128 )
OPCODE(FPVectorNeg64, T::U128, T::U128 )
OPCODE(FPVectorPairedAddLower32, T::U128, T::U128, T::U128 ) OPCODE(FPVectorPairedAddLower32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAddLower64, T::U128, T::U128, T::U128 ) OPCODE(FPVectorPairedAddLower64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd32, T::U128, T::U128, T::U128 ) OPCODE(FPVectorPairedAdd32, T::U128, T::U128, T::U128 )