translate_arm/coprocessor: Minor tidying up
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Lioncash
MerryMage
parent
1e32a09c03
commit
05a6ab691d
1 changed files with 56 additions and 37 deletions
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@ -8,36 +8,40 @@
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namespace Dynarmic::A32 {
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// CDP{2} <coproc_no>, #<opc1>, <CRd>, <CRn>, <CRm>, #<opc2>
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bool ArmTranslatorVisitor::arm_CDP(Cond cond, size_t opc1, CoprocReg CRn, CoprocReg CRd, size_t coproc_no, size_t opc2, CoprocReg CRm) {
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if ((coproc_no & 0b1110) == 0b1010)
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if ((coproc_no & 0b1110) == 0b1010) {
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return arm_UDF();
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}
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const bool two = cond == Cond::NV;
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// CDP{2} <coproc_no>, #<opc1>, <CRd>, <CRn>, <CRm>, #<opc2>
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if (two || ConditionPassed(cond)) {
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ir.CoprocInternalOperation(coproc_no, two, opc1, CRd, CRn, CRm, opc2);
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}
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return true;
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}
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// LDC{2}{L}<c> <coproc_no>, <CRd>, [<Rn>, #+/-<imm32>]{!}
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// LDC{2}{L}<c> <coproc_no>, <CRd>, [<Rn>], #+/-<imm32>
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// LDC{2}{L}<c> <coproc_no>, <CRd>, [<Rn>], <imm8>
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bool ArmTranslatorVisitor::arm_LDC(Cond cond, bool p, bool u, bool d, bool w, Reg n, CoprocReg CRd, size_t coproc_no, Imm8 imm8) {
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if (!p && !u && !d && !w)
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if (!p && !u && !d && !w) {
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return arm_UDF();
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if ((coproc_no & 0b1110) == 0b1010)
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}
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if ((coproc_no & 0b1110) == 0b1010) {
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return arm_UDF();
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}
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const bool two = cond == Cond::NV;
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const u32 imm32 = static_cast<u8>(imm8) << 2;
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const bool index = p;
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const bool add = u;
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const bool wback = w;
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const bool has_option = !p && !w && u;
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// LDC{2}{L} <coproc_no>, <CRd>, [<Rn>, #+/-<imm32>]{!}
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// LDC{2}{L} <coproc_no>, <CRd>, [<Rn>], #+/-<imm32>
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// LDC{2}{L} <coproc_no>, <CRd>, [<Rn>], <imm8>
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if (two || ConditionPassed(cond)) {
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const u32 imm32 = static_cast<u8>(imm8) << 2;
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const bool index = p;
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const bool add = u;
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const bool wback = w;
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const bool has_option = !p && !w && u;
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const IR::U32 reg_n = ir.GetRegister(n);
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const IR::U32 offset_address = add ? ir.Add(reg_n, ir.Imm32(imm32)) : ir.Sub(reg_n, ir.Imm32(imm32));
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const IR::U32 address = index ? offset_address : reg_n;
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@ -49,91 +53,106 @@ bool ArmTranslatorVisitor::arm_LDC(Cond cond, bool p, bool u, bool d, bool w, Re
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return true;
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}
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// MCR{2}<c> <coproc_no>, #<opc1>, <Rt>, <CRn>, <CRm>, #<opc2>
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bool ArmTranslatorVisitor::arm_MCR(Cond cond, size_t opc1, CoprocReg CRn, Reg t, size_t coproc_no, size_t opc2, CoprocReg CRm) {
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if ((coproc_no & 0b1110) == 0b1010)
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if ((coproc_no & 0b1110) == 0b1010) {
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return arm_UDF();
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if (t == Reg::PC)
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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const bool two = cond == Cond::NV;
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// MCR{2} <coproc_no>, #<opc1>, <Rt>, <CRn>, <CRm>, #<opc2>
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if (two || ConditionPassed(cond)) {
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ir.CoprocSendOneWord(coproc_no, two, opc1, CRn, CRm, opc2, ir.GetRegister(t));
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}
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return true;
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}
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// MCRR{2}<c> <coproc_no>, #<opc>, <Rt>, <Rt2>, <CRm>
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bool ArmTranslatorVisitor::arm_MCRR(Cond cond, Reg t2, Reg t, size_t coproc_no, size_t opc, CoprocReg CRm) {
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if ((coproc_no & 0b1110) == 0b1010)
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if ((coproc_no & 0b1110) == 0b1010) {
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return arm_UDF();
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if (t == Reg::PC || t2 == Reg::PC)
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}
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if (t == Reg::PC || t2 == Reg::PC) {
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return UnpredictableInstruction();
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}
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const bool two = cond == Cond::NV;
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// MCRR{2} <coproc_no>, #<opc>, <Rt>, <Rt2>, <CRm>
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if (two || ConditionPassed(cond)) {
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ir.CoprocSendTwoWords(coproc_no, two, opc, CRm, ir.GetRegister(t), ir.GetRegister(t2));
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}
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return true;
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}
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// MRC{2}<c> <coproc_no>, #<opc1>, <Rt>, <CRn>, <CRm>, #<opc2>
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bool ArmTranslatorVisitor::arm_MRC(Cond cond, size_t opc1, CoprocReg CRn, Reg t, size_t coproc_no, size_t opc2, CoprocReg CRm) {
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if ((coproc_no & 0b1110) == 0b1010)
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if ((coproc_no & 0b1110) == 0b1010) {
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return arm_UDF();
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}
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const bool two = cond == Cond::NV;
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// MRC{2} <coproc_no>, #<opc1>, <Rt>, <CRn>, <CRm>, #<opc2>
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if (two || ConditionPassed(cond)) {
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auto word = ir.CoprocGetOneWord(coproc_no, two, opc1, CRn, CRm, opc2);
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const auto word = ir.CoprocGetOneWord(coproc_no, two, opc1, CRn, CRm, opc2);
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if (t != Reg::PC) {
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ir.SetRegister(t, word);
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} else {
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auto new_cpsr_nzcv = ir.And(word, ir.Imm32(0xF0000000));
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const auto new_cpsr_nzcv = ir.And(word, ir.Imm32(0xF0000000));
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ir.SetCpsrNZCV(new_cpsr_nzcv);
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}
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}
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return true;
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}
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// MRRC{2}<c> <coproc_no>, #<opc>, <Rt>, <Rt2>, <CRm>
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bool ArmTranslatorVisitor::arm_MRRC(Cond cond, Reg t2, Reg t, size_t coproc_no, size_t opc, CoprocReg CRm) {
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if ((coproc_no & 0b1110) == 0b1010)
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if ((coproc_no & 0b1110) == 0b1010) {
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return arm_UDF();
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if (t == Reg::PC || t2 == Reg::PC || t == t2)
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}
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if (t == Reg::PC || t2 == Reg::PC || t == t2) {
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return UnpredictableInstruction();
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}
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const bool two = cond == Cond::NV;
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// MRRC{2} <coproc_no>, #<opc>, <Rt>, <Rt2>, <CRm>
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if (two || ConditionPassed(cond)) {
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auto two_words = ir.CoprocGetTwoWords(coproc_no, two, opc, CRm);
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const auto two_words = ir.CoprocGetTwoWords(coproc_no, two, opc, CRm);
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ir.SetRegister(t, ir.LeastSignificantWord(two_words));
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ir.SetRegister(t2, ir.MostSignificantWord(two_words).result);
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}
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return true;
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}
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// STC{2}{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm32>]{!}
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// STC{2}{L}<c> <coproc>, <CRd>, [<Rn>], #+/-<imm32>
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// STC{2}{L}<c> <coproc>, <CRd>, [<Rn>], <imm8>
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bool ArmTranslatorVisitor::arm_STC(Cond cond, bool p, bool u, bool d, bool w, Reg n, CoprocReg CRd, size_t coproc_no, Imm8 imm8) {
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if ((coproc_no & 0b1110) == 0b1010)
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if ((coproc_no & 0b1110) == 0b1010) {
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return arm_UDF();
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if (!p && !u && !d && !w)
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}
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if (!p && !u && !d && !w) {
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return arm_UDF();
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if (n == Reg::PC && w)
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}
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if (n == Reg::PC && w) {
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return UnpredictableInstruction();
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}
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const bool two = cond == Cond::NV;
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const u32 imm32 = static_cast<u8>(imm8) << 2;
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const bool index = p;
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const bool add = u;
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const bool wback = w;
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const bool has_option = !p && !w && u;
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// STC{2}{L} <coproc>, <CRd>, [<Rn>, #+/-<imm32>]{!}
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// STC{2}{L} <coproc>, <CRd>, [<Rn>], #+/-<imm32>
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// STC{2}{L} <coproc>, <CRd>, [<Rn>], <imm8>
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if (two || ConditionPassed(cond)) {
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const u32 imm32 = static_cast<u8>(imm8) << 2;
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const bool index = p;
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const bool add = u;
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const bool wback = w;
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const bool has_option = !p && !w && u;
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const IR::U32 reg_n = ir.GetRegister(n);
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const IR::U32 offset_address = add ? ir.Add(reg_n, ir.Imm32(imm32)) : ir.Sub(reg_n, ir.Imm32(imm32));
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const IR::U32 address = index ? offset_address : reg_n;
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