Merge pull request #485 from lioncash/a32

A32: Handle all ARM-mode arithmetic and data processing instructions added in ARMv6T2 and ARMv7

src/CMakeLists.txt

@@ -98,6 +98,7 @@ add_library(dynarmic
     frontend/A32/translate/translate_arm/branch.cpp
     frontend/A32/translate/translate_arm/coprocessor.cpp
     frontend/A32/translate/translate_arm/data_processing.cpp
+    frontend/A32/translate/translate_arm/divide.cpp
     frontend/A32/translate/translate_arm/exception_generating.cpp
     frontend/A32/translate/translate_arm/extension.cpp
     frontend/A32/translate/translate_arm/load_store.cpp

src/frontend/A32/decoder/arm.inc

@@ -164,9 +164,14 @@ INST(arm_STMIB,         "STMIB",               "cccc100110w0nnnnxxxxxxxxxxxxxxxx
 INST(arm_STM_usr,       "STM (usr reg)",       "----100--100--------------------") // all
 
 // Miscellaneous instructions
+INST(arm_BFC,           "BFC",                 "cccc0111110vvvvvddddvvvvv0011111") // v6T2
+INST(arm_BFI,           "BFI",                 "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
 INST(arm_CLZ,           "CLZ",                 "cccc000101101111dddd11110001mmmm") // v5
+INST(arm_MOVT,          "MOVT",                "cccc00110100vvvvddddvvvvvvvvvvvv") // v6T2
 INST(arm_NOP,           "NOP",                 "----0011001000001111000000000000") // v6K
+INST(arm_SBFX,          "SBFX",                "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2
 INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6
+INST(arm_UBFX,          "UBFX",                "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2
 
 // Unsigned Sum of Absolute Differences instructions
 INST(arm_USAD8,         "USAD8",               "cccc01111000dddd1111mmmm0001nnnn") // v6
@@ -177,6 +182,7 @@ INST(arm_PKHBT,         "PKHBT",               "cccc01101000nnnnddddvvvvv001mmmm
 INST(arm_PKHTB,         "PKHTB",               "cccc01101000nnnnddddvvvvv101mmmm") // v6K
 
 // Reversal instructions
+INST(arm_RBIT,          "RBIT",                "cccc011011111111dddd11110011mmmm") // v6T2
 INST(arm_REV,           "REV",                 "cccc011010111111dddd11110011mmmm") // v6
 INST(arm_REV16,         "REV16",               "cccc011010111111dddd11111011mmmm") // v6
 INST(arm_REVSH,         "REVSH",               "cccc011011111111dddd11111011mmmm") // v6
@@ -187,8 +193,13 @@ INST(arm_SSAT16,        "SSAT16",              "cccc01101010vvvvdddd11110011nnnn
 INST(arm_USAT,          "USAT",                "cccc0110111vvvvvddddvvvvvr01nnnn") // v6
 INST(arm_USAT16,        "USAT16",              "cccc01101110vvvvdddd11110011nnnn") // v6
 
+// Divide instructions
+INST(arm_SDIV,          "SDIV",                "cccc01110001dddd1111mmmm0001nnnn") // v7a
+INST(arm_UDIV,          "UDIV",                "cccc01110011dddd1111mmmm0001nnnn") // v7a
+
 // Multiply (Normal) instructions
 INST(arm_MLA,           "MLA",                 "cccc0000001Sddddaaaammmm1001nnnn") // v2
+INST(arm_MLS,           "MLS",                 "cccc00000110ddddaaaammmm1001nnnn") // v6T2
 INST(arm_MUL,           "MUL",                 "cccc0000000Sdddd0000mmmm1001nnnn") // v2
 
 // Multiply (Long) instructions

src/frontend/A32/disassembler/disassembler_arm.cpp

@@ -583,15 +583,33 @@ public:
     std::string arm_STM_usr() { return "ice"; }
 
     // Miscellaneous instructions
+    std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
+        return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1);
+    }
+    std::string arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) {
+        return fmt::format("bfi{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, msb - lsb + 1);
+    }
     std::string arm_CLZ(Cond cond, Reg d, Reg m) {
         return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
     }
+    std::string arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12) {
+        return fmt::format("movt{} {}, #{}", CondToString(cond), d, (imm4 << 12) | imm12);
+    }
     std::string arm_NOP() {
         return "nop";
     }
+    std::string arm_RBIT(Cond cond, Reg d, Reg m) {
+        return fmt::format("rbit{} {}, {}", CondToString(cond), d, m);
+    }
+    std::string arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
+        return fmt::format("sbfx{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, widthm1 + 1);
+    }
     std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
         return fmt::format("sel{} {}, {}, {}", CondToString(cond), d, n, m);
     }
+    std::string arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
+        return fmt::format("ubfx{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, widthm1 + 1);
+    }
 
     // Unsigned sum of absolute difference functions
     std::string arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {
@@ -634,10 +652,21 @@ public:
         return fmt::format("usat16{} {}, #{}, {}", CondToString(cond), d, sat_imm, n);
     }
 
+    // Divide instructions
+    std::string arm_SDIV(Cond cond, Reg d, Reg m, Reg n) {
+        return fmt::format("sdiv{} {}, {}, {}", CondToString(cond), d, n, m);
+    }
+    std::string arm_UDIV(Cond cond, Reg d, Reg m, Reg n) {
+        return fmt::format("udiv{} {}, {}, {}", CondToString(cond), d, n, m);
+    }
+
     // Multiply (Normal) instructions
     std::string arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n) {
         return fmt::format("mla{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), d, n, m, a);
     }
+    std::string arm_MLS(Cond cond, Reg d, Reg a, Reg m, Reg n) {
+        return fmt::format("mls{} {}, {}, {}, {}", CondToString(cond), d, n, m, a);
+    }
     std::string arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) {
         return fmt::format("mul{}{} {}, {}, {}", S ? "s" : "", CondToString(cond), d, n, m);
     }

src/frontend/A32/translate/translate_arm/divide.cpp

@@ -0,0 +1,42 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2019 MerryMage
+ * This software may be used and distributed according to the terms of the GNU
+ * General Public License version 2 or any later version.
+ */
+
+#include "translate_arm.h"
+
+namespace Dynarmic::A32 {
+namespace {
+using DivideFunction = IR::U32U64 (IREmitter::*)(const IR::U32U64&, const IR::U32U64&);
+
+bool DivideOperation(ArmTranslatorVisitor& v, Cond cond, Reg d, Reg m, Reg n,
+                     DivideFunction fn) {
+    if (d == Reg::PC || m == Reg::PC || n == Reg::PC) {
+        return v.UnpredictableInstruction();
+    }
+
+    if (!v.ConditionPassed(cond)) {
+        return true;
+    }
+
+    const IR::U32 operand1 = v.ir.GetRegister(n);
+    const IR::U32 operand2 = v.ir.GetRegister(m);
+    const IR::U32 result = (v.ir.*fn)(operand1, operand2);
+
+    v.ir.SetRegister(d, result);
+    return true;
+}
+} // Anonymous namespace
+
+// SDIV<c> <Rd>, <Rn>, <Rm>
+bool ArmTranslatorVisitor::arm_SDIV(Cond cond, Reg d, Reg m, Reg n) {
+    return DivideOperation(*this, cond, d, m, n, &IREmitter::SignedDiv);
+}
+
+// UDIV<c> <Rd>, <Rn>, <Rm>
+bool ArmTranslatorVisitor::arm_UDIV(Cond cond, Reg d, Reg m, Reg n) {
+    return DivideOperation(*this, cond, d, m, n, &IREmitter::UnsignedDiv);
+}
+
+} // namespace Dynarmic::A32

src/frontend/A32/translate/translate_arm/misc.cpp

@@ -4,10 +4,55 @@
  * General Public License version 2 or any later version.
  */
 
+#include "common/bit_util.h"
 #include "translate_arm.h"
 
 namespace Dynarmic::A32 {
 
+// BFC<c> <Rd>, #<lsb>, #<width>
+bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
+    if (d == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+    if (msb < lsb) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const u32 mask = ~(Common::Ones<u32>(msb - lsb + 1) << lsb);
+    const IR::U32 operand = ir.GetRegister(d);
+    const IR::U32 result = ir.And(operand, ir.Imm32(mask));
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
+// BFI<c> <Rd>, <Rn>, #<lsb>, #<width>
+bool ArmTranslatorVisitor::arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) {
+    if (d == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+    if (msb < lsb) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const u32 inclusion_mask = Common::Ones<u32>(msb - lsb + 1) << lsb;
+    const u32 exclusion_mask = ~inclusion_mask;
+    const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask));
+    const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(lsb)), ir.Imm32(inclusion_mask));
+    const IR::U32 result = ir.Or(operand1, operand2);
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 // CLZ<c> <Rd>, <Rm>
 bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
     if (d == Reg::PC || m == Reg::PC) {
@@ -22,6 +67,51 @@ bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
     return true;
 }
 
+// MOVT<c> <Rd>, #<imm16>
+bool ArmTranslatorVisitor::arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12) {
+    if (d == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const IR::U32 imm16 = ir.Imm32(((u32(imm4) << 12 | u32(imm12)) << 16));
+    const IR::U32 operand = ir.GetRegister(d);
+    const IR::U32 result = ir.Or(ir.And(operand, ir.Imm32(0x0000FFFFU)), imm16);
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
+// SBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
+bool ArmTranslatorVisitor::arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
+    if (d == Reg::PC || n == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    const u32 msb = u32{lsb} + widthm1;
+    if (msb >= Common::BitSize<u32>()) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    constexpr size_t max_width = Common::BitSize<u32>();
+    const u8 width = widthm1 + 1;
+    const u8 left_shift_amount = static_cast<u8>(max_width - width - lsb);
+    const u8 right_shift_amount = static_cast<u8>(max_width - width);
+    const IR::U32 operand = ir.GetRegister(n);
+    const IR::U32 tmp = ir.LogicalShiftLeft(operand, ir.Imm8(left_shift_amount));
+    const IR::U32 result = ir.ArithmeticShiftRight(tmp, ir.Imm8(right_shift_amount));
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 // SEL<c> <Rd>, <Rn>, <Rm>
 bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
     if (n == Reg::PC || d == Reg::PC || m == Reg::PC) {
@@ -40,4 +130,27 @@ bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
     return true;
 }
 
+// UBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
+bool ArmTranslatorVisitor::arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
+    if (d == Reg::PC || n == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    const u32 msb = u32{lsb} + widthm1;
+    if (msb >= Common::BitSize<u32>()) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const IR::U32 operand = ir.GetRegister(n);
+    const IR::U32 mask = ir.Imm32(Common::Ones<u32>(widthm1 + 1));
+    const IR::U32 result = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(lsb)), mask);
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 } // namespace Dynarmic::A32

src/frontend/A32/translate/translate_arm/multiply.cpp

@@ -28,6 +28,25 @@ bool ArmTranslatorVisitor::arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n
     return true;
 }
 
+// MLS<c> <Rd>, <Rn>, <Rm>, <Ra>
+bool ArmTranslatorVisitor::arm_MLS(Cond cond, Reg d, Reg a, Reg m, Reg n) {
+    if (d == Reg::PC || a == Reg::PC || m == Reg::PC || n == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const IR::U32 operand1 = ir.GetRegister(n);
+    const IR::U32 operand2 = ir.GetRegister(m);
+    const IR::U32 operand3 = ir.GetRegister(a);
+    const IR::U32 result = ir.Sub(operand3, ir.Mul(operand1, operand2));
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 // MUL{S}<c> <Rd>, <Rn>, <Rm>
 bool ArmTranslatorVisitor::arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) {
     if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {

src/frontend/A32/translate/translate_arm/reversal.cpp

@@ -8,6 +8,36 @@
 
 namespace Dynarmic::A32 {
 
+// RBIT<c> <Rd>, <Rm>
+bool ArmTranslatorVisitor::arm_RBIT(Cond cond, Reg d, Reg m) {
+    if (d == Reg::PC || m == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const IR::U32 swapped = ir.ByteReverseWord(ir.GetRegister(m));
+
+    // ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4)
+    const IR::U32 first_lsr = ir.LogicalShiftRight(ir.And(swapped, ir.Imm32(0xF0F0F0F0)), ir.Imm8(4));
+    const IR::U32 first_lsl = ir.LogicalShiftLeft(ir.And(swapped, ir.Imm32(0x0F0F0F0F)), ir.Imm8(4));
+    const IR::U32 corrected = ir.Or(first_lsl, first_lsr);
+
+    // ((x & 0x88888888) >> 3) | ((x & 0x44444444) >> 1) |
+    // ((x & 0x22222222) << 1) | ((x & 0x11111111) << 3)
+    const IR::U32 second_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x88888888)), ir.Imm8(3));
+    const IR::U32 third_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x44444444)), ir.Imm8(1));
+    const IR::U32 second_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x22222222)), ir.Imm8(1));
+    const IR::U32 third_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x11111111)), ir.Imm8(3));
+
+    const IR::U32 result = ir.Or(ir.Or(ir.Or(second_lsr, third_lsr), second_lsl), third_lsl);
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 // REV<c> <Rd>, <Rm>
 bool ArmTranslatorVisitor::arm_REV(Cond cond, Reg d, Reg m) {
     if (d == Reg::PC || m == Reg::PC) {

src/frontend/A32/translate/translate_arm/translate_arm.h

@@ -207,9 +207,15 @@ struct ArmTranslatorVisitor final {
     bool arm_STM_usr();
 
     // Miscellaneous instructions
+    bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb);
+    bool arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n);
     bool arm_CLZ(Cond cond, Reg d, Reg m);
+    bool arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12);
     bool arm_NOP() { return true; }
+    bool arm_RBIT(Cond cond, Reg d, Reg m);
+    bool arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n);
     bool arm_SEL(Cond cond, Reg n, Reg d, Reg m);
+    bool arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n);
 
     // Unsigned sum of absolute difference functions
     bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n);
@@ -230,8 +236,13 @@ struct ArmTranslatorVisitor final {
     bool arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n);
     bool arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n);
 
+    // Divide instructions
+    bool arm_SDIV(Cond cond, Reg d, Reg m, Reg n);
+    bool arm_UDIV(Cond cond, Reg d, Reg m, Reg n);
+
     // Multiply (Normal) instructions
     bool arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n);
+    bool arm_MLS(Cond cond, Reg d, Reg a, Reg m, Reg n);
     bool arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n);
 
     // Multiply (Long) instructions

tests/A32/fuzz_arm.cpp

@@ -763,9 +763,10 @@ TEST_CASE("Fuzz ARM reversal instructions", "[JitX64][A32]") {
     };
 
     const std::array rev_instructions = {
-        InstructionGenerator("cccc011010111111dddd11110011mmmm", is_valid),
+        InstructionGenerator("cccc011011111111dddd11110011mmmm", is_valid), // RBIT
-        InstructionGenerator("cccc011010111111dddd11111011mmmm", is_valid),
+        InstructionGenerator("cccc011010111111dddd11110011mmmm", is_valid), // REV
-        InstructionGenerator("cccc011011111111dddd11111011mmmm", is_valid),
+        InstructionGenerator("cccc011010111111dddd11111011mmmm", is_valid), // REV16
+        InstructionGenerator("cccc011011111111dddd11111011mmmm", is_valid), // REVSH
     };
 
     SECTION("Reverse tests") {
@@ -812,6 +813,24 @@ TEST_CASE("Fuzz ARM extension instructions", "[JitX64][A32]") {
     }
 }
 
+TEST_CASE("Fuzz ARM divide instructions", "[JitX64][A32]") {
+    const auto is_valid = [](u32 instr) {
+        return Bits<0, 3>(instr) != 0b1111 &&
+               Bits<8, 11>(instr) != 0b1111 &&
+               Bits<16, 19>(instr) != 0b1111;
+    };
+
+    const std::array instructions = {
+        InstructionGenerator("cccc01110001dddd1111mmmm0001nnnn", is_valid), // SDIV
+        InstructionGenerator("cccc01110011dddd1111mmmm0001nnnn", is_valid), // UDIV
+    };
+
+    FuzzJitArm(1, 1, 5000, [&instructions]() -> u32 {
+        return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
+    });
+}
+
+
 TEST_CASE("Fuzz ARM multiply instructions", "[JitX64][A32]") {
     const auto validate_d_m_n = [](u32 inst) -> bool {
         return Bits<16, 19>(inst) != 15 &&
@@ -829,6 +848,7 @@ TEST_CASE("Fuzz ARM multiply instructions", "[JitX64][A32]") {
 
     const std::array instructions = {
         InstructionGenerator("cccc0000001Sddddaaaammmm1001nnnn", validate_d_a_m_n), // MLA
+        InstructionGenerator("cccc00000110ddddaaaammmm1001nnnn", validate_d_a_m_n), // MLS
         InstructionGenerator("cccc0000000Sdddd0000mmmm1001nnnn", validate_d_m_n),   // MUL
 
         InstructionGenerator("cccc0000111Sddddaaaammmm1001nnnn", validate_h_l_m_n), // SMLAL
@@ -1061,18 +1081,45 @@ TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][.vfp][A32]") {
 }
 
 TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
-    const auto is_clz_valid = [](u32 instr) -> bool {
+    const auto is_bfc_bfi_valid = [](u32 instr) {
+        if (Bits<12, 15>(instr) == 0b1111) {
+            // Destination register may not be the PC.
+            return false;
+        }
+        // msb must be greater than or equal to the lsb,
+        // otherwise the instruction is UNPREDICTABLE.
+        return Bits<16, 20>(instr) >= Bits<7, 11>(instr);
+    };
+    const auto is_clz_valid = [](u32 instr) {
         // R15 as Rd, or Rm is UNPREDICTABLE
         return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111;
     };
+    const auto is_extract_valid = [](u32 instr) {
+        const u32 lsb = Bits<7, 11>(instr);
+        const u32 widthm1 = Bits<16, 20>(instr);
+        const u32 msb = lsb + widthm1;
 
-    const InstructionGenerator clz_instr = InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid); // CLZ
+        // Rd or Rn as R15 or the case where msb > 32 is UNPREDICTABLE.
+        return Bits<0, 3>(instr) != 0b1111 &&
+               Bits<12, 15>(instr) != 0b1111 &&
+               msb < Dynarmic::Common::BitSize<u32>();
+    };
+    const auto is_movt_valid = [](u32 instr) {
+        return Bits<12, 15>(instr) != 0b1111;
+    };
 
-    SECTION("Fuzz CLZ") {
+    const std::array instructions = {
-        FuzzJitArm(1, 1, 1000, [&clz_instr]() -> u32 {
+        InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC
-            return clz_instr.Generate();
+        InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI
-        });
+        InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid),     // CLZ
-    }
+        InstructionGenerator("cccc00110100vvvvddddvvvvvvvvvvvv", is_movt_valid),    // MOVT
+        InstructionGenerator("cccc0111101wwwwwddddvvvvv101nnnn", is_extract_valid), // SBFX
+        InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_extract_valid), // UBFX
+    };
+
+    FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {
+        return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
+    });
 }
 
 TEST_CASE("Test ARM MSR instructions", "[JitX64][A32]") {