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A64: Implement half-precision scalar variant of FRECPE

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Lioncash 2019-04-13 19:07:01 -04:00 committed by MerryMage
parent 86b7626a2f
commit 0945a491bd
2 changed files with 11 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -418,7 +418,7 @@ INST(FCMLT_2, "FCMLT (zero)", "01011
INST(FCVTPS_2, "FCVTPS (vector)", "010111101z100001101010nnnnnddddd")
//INST(FCVTZS_int_1, "FCVTZS (vector, integer)", "0101111011111001101110nnnnnddddd")
INST(FCVTZS_int_2, "FCVTZS (vector, integer)", "010111101z100001101110nnnnnddddd")
//INST(FRECPE_1, "FRECPE", "0101111011111001110110nnnnnddddd")
INST(FRECPE_1, "FRECPE", "0101111011111001110110nnnnnddddd")
INST(FRECPE_2, "FRECPE", "010111101z100001110110nnnnnddddd")
INST(FRECPX_1, "FRECPX", "0101111011111001111110nnnnnddddd")
INST(FRECPX_2, "FRECPX", "010111101z100001111110nnnnnddddd")

10
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
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@ -172,6 +172,16 @@ bool TranslatorVisitor::FCVTZU_int_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Unsigned);
}
bool TranslatorVisitor::FRECPE_1(Vec Vn, Vec Vd) {
const size_t esize = 16;
const IR::U16 operand = V_scalar(esize, Vn);
const IR::U16 result = ir.FPRecipEstimate(operand);
V_scalar(esize, Vd, result);
return true;
}
bool TranslatorVisitor::FRECPE_2(bool sz, Vec Vn, Vec Vd) {
const size_t esize = sz ? 64 : 32;