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A64: Implement SHLL/SHLL2

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Lioncash 2018-05-08 10:14:06 -04:00 committed by MerryMage
parent 43e6e98c3b
commit 0e61ee6bf6
2 changed files with 15 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -623,7 +623,7 @@ INST(CMGE_zero_2, "CMGE (zero)", "0Q101
INST(CMLE_2, "CMLE (zero)", "0Q101110zz100000100110nnnnnddddd")
INST(NEG_2, "NEG (vector)", "0Q101110zz100000101110nnnnnddddd")
//INST(SQXTUN_2, "SQXTUN, SQXTUN2", "0Q101110zz100001001010nnnnnddddd")
//INST(SHLL, "SHLL, SHLL2", "0Q101110zz100001001110nnnnnddddd")
INST(SHLL, "SHLL, SHLL2", "0Q101110zz100001001110nnnnnddddd")
//INST(UQXTN_2, "UQXTN, UQXTN2", "0Q101110zz100001010010nnnnnddddd")
//INST(FCVTXN_2, "FCVTXN, FCVTXN2", "0Q1011100z100001011010nnnnnddddd")
//INST(FRINTA_1, "FRINTA (vector)", "0Q10111001111001100010nnnnnddddd")

14
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -281,4 +281,18 @@ bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SHLL(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const IR::U128 operand = ir.VectorZeroExtend(esize, Vpart(64, Vn, Q));
const IR::U128 result = ir.VectorLogicalShiftLeft(esize * 2, operand, static_cast<u8>(esize));
V(128, Vd, result);
return true;
}
} // namespace Dynarmic::A64