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A64: Add hook_isb option

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MerryMage 2021-01-26 23:41:21 +00:00
parent 3806284cbe
commit 0f27368fda
2 changed files with 12 additions and 4 deletions
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6
include/dynarmic/A64/config.h
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@ -110,6 +110,7 @@ struct UserCallbacks {
virtual void ExceptionRaised(VAddr pc, Exception exception) = 0;
virtual void DataCacheOperationRaised(DataCacheOperation /*op*/, VAddr /*value*/) {}
virtual void InstructionSynchronizationBarrierRaised() {}
// Timing-related callbacks
// ticks ticks have passed
@ -153,6 +154,11 @@ struct UserConfig {
/// Executing DC ZVA in this mode will result in zeros being written to memory.
bool hook_data_cache_operations = false;
/// When set to true, UserCallbacks::InstructionSynchronizationBarrierRaised will be
/// called when an ISB instruction is executed.
/// When set to false, ISB will be treated as a NOP instruction.
bool hook_isb = false;
/// When set to true, UserCallbacks::ExceptionRaised will be called when any hint
/// instruction is executed.
bool hook_hint_instructions = false;

8
src/backend/x64/a64_emit_x64.cpp
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@ -660,10 +660,12 @@ void A64EmitX64::EmitA64DataMemoryBarrier(A64EmitContext&, IR::Inst*) {
}
void A64EmitX64::EmitA64InstructionSynchronizationBarrier(A64EmitContext& ctx, IR::Inst*) {
ctx.reg_alloc.HostCall(nullptr);
if (!conf.hook_isb) {
return;
}
code.mov(code.ABI_PARAM1, reinterpret_cast<u64>(jit_interface));
code.CallLambda([](A64::Jit* jit) { jit->ClearCache(); });
ctx.reg_alloc.HostCall(nullptr);
Devirtualize<&A64::UserCallbacks::InstructionSynchronizationBarrierRaised>(conf.callbacks).EmitCall(code);
}
void A64EmitX64::EmitA64GetCNTFRQ(A64EmitContext& ctx, IR::Inst* inst) {