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IR: Implement VectorNarrow

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This commit is contained in:
MerryMage 2018-02-10 16:47:36 +00:00
parent 1423584f9f
commit 132c783320
4 changed files with 58 additions and 0 deletions
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41
src/backend_x64/emit_x64_vector.cpp
View file

@ -414,6 +414,47 @@ void EmitX64::EmitVectorInterleaveLower64(EmitContext& ctx, IR::Inst* inst) {
EmitVectorInterleaveLower(code, ctx, inst, 64);
}
void EmitX64::EmitVectorNarrow16(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
Xbyak::Xmm zeros = ctx.reg_alloc.ScratchXmm();
// TODO: AVX512F implementation
code.pxor(zeros, zeros);
code.pand(a, code.MConst(0x00FF00FF00FF00FF, 0x00FF00FF00FF00FF));
code.packuswb(a, zeros);
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitVectorNarrow32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
Xbyak::Xmm zeros = ctx.reg_alloc.ScratchXmm();
// TODO: AVX512F implementation
code.pxor(zeros, zeros);
code.pand(a, code.MConst(0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF));
code.packusdw(a, zeros);
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitVectorNarrow64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
Xbyak::Xmm zeros = ctx.reg_alloc.ScratchXmm();
// TODO: AVX512F implementation
code.pxor(zeros, zeros);
code.shufps(a, zeros, 0b00001000);
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitVectorNot(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);

13
src/frontend/ir/ir_emitter.cpp
View file

@ -898,6 +898,19 @@ U128 IREmitter::VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_am
return {};
}
U128 IREmitter::VectorNarrow(size_t original_esize, const U128& a) {
switch (original_esize) {
case 16:
return Inst<U128>(Opcode::VectorNarrow16, a);
case 32:
return Inst<U128>(Opcode::VectorNarrow32, a);
case 64:
return Inst<U128>(Opcode::VectorNarrow64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorNot(const U128& a) {
return Inst<U128>(Opcode::VectorNot, a);
}

1
src/frontend/ir/ir_emitter.h
View file

@ -216,6 +216,7 @@ public:
U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b);
U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount);
U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount);
U128 VectorNarrow(size_t original_esize, const U128& a);
U128 VectorNot(const U128& a);
U128 VectorOr(const U128& a, const U128& b);
U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b);

3
src/frontend/ir/opcodes.inc
View file

@ -228,6 +228,9 @@ OPCODE(VectorLogicalShiftRight8, T::U128, T::U128, T::U8
OPCODE(VectorLogicalShiftRight16, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight32, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight64, T::U128, T::U128, T::U8 )
OPCODE(VectorNarrow16, T::U128, T::U128 )
OPCODE(VectorNarrow32, T::U128, T::U128 )
OPCODE(VectorNarrow64, T::U128, T::U128 )
OPCODE(VectorNot, T::U128, T::U128 )
OPCODE(VectorOr, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower8, T::U128, T::U128, T::U128 )