emit_x64_vector: SSE implementation of VectorSignedSaturatedAccumulateUnsigned{8,16,32}
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MerryMage
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26df6e5e7b
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1492573267
1 changed files with 106 additions and 72 deletions
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@ -2810,49 +2810,8 @@ void EmitX64::EmitVectorSignedSaturatedAbs64(EmitContext& ctx, IR::Inst* inst) {
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});
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});
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}
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}
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// Simple generic case for 8, 16, and 32-bit values. 64-bit values
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template<size_t bit_width>
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// will need to be special-cased as we can't simply use a larger integral size.
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static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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template <typename T>
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static bool EmitSignedSaturatedAccumulateUnsigned(VectorArray<T>& result, const VectorArray<T>& lhs, const VectorArray<T>& rhs) {
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static_assert(std::is_signed_v<T>, "T must be signed.");
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static_assert(Common::BitSize<T>() < 64, "T must be less than 64 bits in size.");
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bool qc_flag = false;
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for (size_t i = 0; i < result.size(); i++) {
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// We treat lhs' members as unsigned, so cast to unsigned before signed to inhibit sign-extension.
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// We use the unsigned equivalent of T, as we want zero-extension to occur, rather than a plain move.
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const s64 x = static_cast<s64>(static_cast<std::make_unsigned_t<T>>(lhs[i]));
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const s64 y = rhs[i];
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const s64 sum = x + y;
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if (sum > std::numeric_limits<T>::max()) {
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result[i] = std::numeric_limits<T>::max();
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qc_flag = true;
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} else if (sum < std::numeric_limits<T>::min()) {
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result[i] = std::numeric_limits<T>::min();
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qc_flag = true;
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} else {
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result[i] = static_cast<T>(sum);
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}
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}
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return qc_flag;
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}
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void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned8(EmitContext& ctx, IR::Inst* inst) {
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EmitTwoArgumentFallbackWithSaturation(code, ctx, inst, EmitSignedSaturatedAccumulateUnsigned<s8>);
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}
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void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned16(EmitContext& ctx, IR::Inst* inst) {
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EmitTwoArgumentFallbackWithSaturation(code, ctx, inst, EmitSignedSaturatedAccumulateUnsigned<s16>);
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}
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void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned32(EmitContext& ctx, IR::Inst* inst) {
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EmitTwoArgumentFallbackWithSaturation(code, ctx, inst, EmitSignedSaturatedAccumulateUnsigned<s32>);
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}
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void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned64(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(args[1]);
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@ -2863,52 +2822,111 @@ void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned64(EmitContext& ctx, IR
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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switch (bit_width) {
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case 8:
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vpaddb(result, x, xmm0);
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} else {
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code.movdqa(result, x);
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code.paddb(result, xmm0);
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}
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break;
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case 16:
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vpaddw(result, x, xmm0);
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} else {
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code.movdqa(result, x);
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code.paddw(result, xmm0);
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}
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break;
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case 32:
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vpaddd(result, x, xmm0);
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} else {
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code.movdqa(result, x);
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code.paddd(result, xmm0);
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}
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break;
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case 64:
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vpaddq(result, x, xmm0);
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code.vpaddq(result, x, xmm0);
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} else {
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} else {
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code.movdqa(result, x);
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code.movdqa(result, x);
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code.paddq(result, xmm0);
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code.paddq(result, xmm0);
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}
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}
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break;
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}
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
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// xmm0 = majority(~y, x, res)
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// xmm0 = majority(~y, x, res)
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// y x res xmm0
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// 0 0 0 0
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// 0 0 1 1
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// 0 1 0 1
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// 0 1 1 1
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// 1 0 0 0
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// 1 0 1 0
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// 1 1 0 0
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// 1 1 1 1
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code.vpternlogd(xmm0, x, result, 0b10001110);
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code.vpternlogd(xmm0, x, result, 0b10001110);
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code.vpsraq(xmm0, xmm0, 63);
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code.movdqa(tmp, xmm0);
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} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vpor(tmp, x, result);
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code.vpor(tmp, x, result);
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code.pand(x, result);
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code.pand(x, result);
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code.pblendvb(tmp, x);
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code.vpblendvb(xmm0, tmp, x, xmm0);
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code.psrad(tmp, 31);
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code.pshufd(tmp, tmp, 0b11110101);
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code.movdqa(xmm0, tmp);
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} else {
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} else {
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code.movdqa(tmp, x);
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code.movdqa(tmp, x);
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code.por(tmp, result);
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code.pxor(x, result);
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code.pand(x, result);
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code.pand(tmp, result);
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code.pand(x, xmm0);
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code.pandn(xmm0, x);
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code.pandn(xmm0, tmp);
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code.por(xmm0, tmp);
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code.por(xmm0, x);
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}
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ctx.reg_alloc.Release(x);
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switch (bit_width) {
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case 8:
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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const Xbyak::Xmm tmp2 = ctx.reg_alloc.ScratchXmm();
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code.pcmpeqb(tmp2, tmp2);
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code.pxor(tmp, tmp);
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code.vpblendvb(xmm0, tmp, tmp2, xmm0);
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ctx.reg_alloc.Release(tmp2);
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} else {
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code.pand(xmm0, code.MConst(xword, 0x8080808080808080, 0x8080808080808080));
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code.movdqa(tmp, xmm0);
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code.psrlw(tmp, 7);
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code.pxor(xmm0, xmm0);
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code.psubb(xmm0, tmp);
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}
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break;
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case 16:
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code.psraw(xmm0, 15);
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break;
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case 32:
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code.psrad(xmm0, 31);
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break;
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case 64:
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
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code.vpsraq(xmm0, xmm0, 63);
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} else {
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code.psrad(xmm0, 31);
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code.psrad(xmm0, 31);
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code.pshufd(xmm0, xmm0, 0b11110101);
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code.pshufd(xmm0, xmm0, 0b11110101);
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}
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break;
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}
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code.movdqa(tmp, xmm0);
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code.movdqa(tmp, xmm0);
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switch (bit_width) {
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case 8:
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code.paddb(tmp, tmp);
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code.psrlw(tmp, 1);
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break;
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case 16:
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code.psrlw(tmp, 1);
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break;
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case 32:
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code.psrld(tmp, 1);
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break;
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case 64:
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code.psrlq(tmp, 1);
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break;
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}
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}
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const Xbyak::Reg32 mask = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 mask = ctx.reg_alloc.ScratchGpr().cvt32();
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code.pmovmskb(mask, xmm0);
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code.pmovmskb(mask, xmm0);
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code.or_(code.dword[code.r15 + code.GetJitStateInfo().offsetof_fpsr_qc], mask);
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code.or_(code.dword[code.r15 + code.GetJitStateInfo().offsetof_fpsr_qc], mask);
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code.psrlq(tmp, 1);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.pblendvb(result, tmp);
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code.pblendvb(result, tmp);
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} else {
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} else {
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@ -2920,6 +2938,22 @@ void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned64(EmitContext& ctx, IR
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ctx.reg_alloc.DefineValue(inst, result);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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}
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void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned8(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSignedSaturatedAccumulateUnsigned<8>(code, ctx, inst);
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}
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void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned16(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSignedSaturatedAccumulateUnsigned<16>(code, ctx, inst);
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}
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void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned32(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSignedSaturatedAccumulateUnsigned<32>(code, ctx, inst);
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}
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void EmitX64::EmitVectorSignedSaturatedAccumulateUnsigned64(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSignedSaturatedAccumulateUnsigned<64>(code, ctx, inst);
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}
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void EmitX64::EmitVectorSignedSaturatedDoublingMultiplyReturnHigh16(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitVectorSignedSaturatedDoublingMultiplyReturnHigh16(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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