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A64: Implement USQADD's scalar and vector variants

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Lioncash 2018-09-09 03:11:19 -04:00 committed by MerryMage
parent d4a76aaa04
commit 14e026a7f0
3 changed files with 30 additions and 2 deletions
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4
src/frontend/A64/decoder/a64.inc
View file

@ -413,7 +413,7 @@ INST(CMEQ_zero_1, "CMEQ (zero)", "01011
INST(CMLT_1, "CMLT (zero)", "01011110zz100000101010nnnnnddddd") INST(CMLT_1, "CMLT (zero)", "01011110zz100000101010nnnnnddddd")
INST(ABS_1, "ABS", "01011110zz100000101110nnnnnddddd") INST(ABS_1, "ABS", "01011110zz100000101110nnnnnddddd")
INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd") INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd")
//INST(USQADD_1, "USQADD", "01111110zz100000001110nnnnnddddd") INST(USQADD_1, "USQADD", "01111110zz100000001110nnnnnddddd")
INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd") INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd")
INST(CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd") INST(CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd")
INST(CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd") INST(CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd")
@ -615,7 +615,7 @@ INST(URECPE, "URECPE", "0Q001
INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd") INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd")
INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd") INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd") INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd")
//INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd") INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd")
//INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd") //INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd")
INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd") INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd")
INST(SQNEG_2, "SQNEG", "0Q101110zz100000011110nnnnnddddd") INST(SQNEG_2, "SQNEG", "0Q101110zz100000011110nnnnnddddd")

12
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -262,4 +262,16 @@ bool TranslatorVisitor::UQXTN_1(Imm<2> size, Vec Vn, Vec Vd) {
return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorUnsignedSaturatedNarrow); return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorUnsignedSaturatedNarrow);
} }
bool TranslatorVisitor::USQADD_1(Imm<2> size, Vec Vn, Vec Vd) {
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = 64;
const IR::U128 operand1 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(datasize, Vn), 0));
const IR::U128 operand2 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(datasize, Vd), 0));
const IR::U128 result = ir.VectorUnsignedSaturatedAccumulateSigned(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64

16
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -645,6 +645,22 @@ bool TranslatorVisitor::SUQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::USQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vd);
const IR::U128 result = ir.VectorUnsignedSaturatedAccumulateSigned(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) { bool TranslatorVisitor::SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Signed, PairedAddLongExtraBehavior::Accumulate); return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Signed, PairedAddLongExtraBehavior::Accumulate);
} }