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Implemented BSL, BIC, BIT and BIF vector instructions

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FernandoS27 2018-01-27 14:23:55 -04:00 committed by MerryMage
parent 7a87e3fc55
commit 15871910af
2 changed files with 50 additions and 3 deletions
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6
src/frontend/A64/decoder/a64.inc
View file

@ -787,15 +787,15 @@ INST(CMEQ_reg_2, "CMEQ (register)", "0Q101
//INST(FMAXP_vec_2, "FMAXP (vector)", "0Q1011100z1mmmmm111101nnnnnddddd") //INST(FMAXP_vec_2, "FMAXP (vector)", "0Q1011100z1mmmmm111101nnnnnddddd")
//INST(FDIV_2, "FDIV (vector)", "0Q1011100z1mmmmm111111nnnnnddddd") //INST(FDIV_2, "FDIV (vector)", "0Q1011100z1mmmmm111111nnnnnddddd")
INST(EOR_asimd, "EOR (vector)", "0Q101110001mmmmm000111nnnnnddddd") INST(EOR_asimd, "EOR (vector)", "0Q101110001mmmmm000111nnnnnddddd")
//INST(BSL, "BSL", "0Q101110011mmmmm000111nnnnnddddd") INST(BSL, "BSL", "0Q101110011mmmmm000111nnnnnddddd")
//INST(FMINNMP_vec_2, "FMINNMP (vector)", "0Q1011101z1mmmmm110001nnnnnddddd") //INST(FMINNMP_vec_2, "FMINNMP (vector)", "0Q1011101z1mmmmm110001nnnnnddddd")
//INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd") //INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd")
//INST(FABD_4, "FABD", "0Q1011101z1mmmmm110101nnnnnddddd") //INST(FABD_4, "FABD", "0Q1011101z1mmmmm110101nnnnnddddd")
//INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd") //INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd")
//INST(FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd") //INST(FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd")
//INST(FMINP_vec_2, "FMINP (vector)", "0Q1011101z1mmmmm111101nnnnnddddd") //INST(FMINP_vec_2, "FMINP (vector)", "0Q1011101z1mmmmm111101nnnnnddddd")
//INST(BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd") INST(BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd")
//INST(BIF, "BIF", "0Q101110111mmmmm000111nnnnnddddd") INST(BIF, "BIF", "0Q101110111mmmmm000111nnnnnddddd")
// Data Processing - FP and SIMD - SIMD modified immediate // Data Processing - FP and SIMD - SIMD modified immediate
INST(MOVI, "MOVI, MVNI, ORR, BIC (vector, immediate)", "0Qo0111100000abcmmmm01defghddddd") INST(MOVI, "MOVI, MVNI, ORR, BIC (vector, immediate)", "0Qo0111100000abcmmmm01defghddddd")

47
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -80,11 +80,13 @@ bool TranslatorVisitor::BIC_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand2 = V(datasize, Vm); const IR::U128 operand2 = V(datasize, Vm);
IR::U128 result = ir.VectorAnd(operand1, ir.VectorNot(operand2)); IR::U128 result = ir.VectorAnd(operand1, ir.VectorNot(operand2));
if (datasize == 64) { if (datasize == 64) {
result = ir.VectorZeroUpper(result); result = ir.VectorZeroUpper(result);
} }
V(datasize, Vd, result); V(datasize, Vd, result);
return true; return true;
} }
@ -161,4 +163,49 @@ bool TranslatorVisitor::EOR_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::BIF(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
auto operand1 = V(datasize, Vd);
auto operand4 = V(datasize, Vn);
auto operand3 = ir.VectorNot(V(datasize, Vm));
auto result = ir.VectorEor(operand1,
ir.VectorAnd(ir.VectorEor(operand1, operand4), operand3));
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::BIT(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
auto operand1 = V(datasize, Vd);
auto operand4 = V(datasize, Vn);
auto operand3 = V(datasize, Vm);
auto result = ir.VectorEor(operand1,
ir.VectorAnd(ir.VectorEor(operand1, operand4), operand3));
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::BSL(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
auto operand4 = V(datasize, Vn);
auto operand1 = V(datasize, Vm);
auto operand3 = V(datasize, Vd);
auto result = ir.VectorEor(operand1,
ir.VectorAnd(ir.VectorEor(operand1, operand4), operand3));
V(datasize, Vd, result);
return true;
}
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64