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A32: Implement VNEG

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Lioncash 2020-06-15 18:25:52 -04:00 committed by merry
parent 2796a85096
commit 15b3de95e4
3 changed files with 28 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -93,7 +93,7 @@ INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd001
//INST(asimd_VCLE_zero, "VCLE (zero)", "111100111-11--01----0x011x-0----") // ASIMD
//INST(asimd_VCLT_zero, "VCLT (zero)", "111100111-11--01----0x100x-0----") // ASIMD
//INST(asimd_VABS, "VABS", "111100111-11--01----0x110x-0----") // ASIMD
//INST(asimd_VNEG, "VNEG", "111100111-11--01----0x111x-0----") // ASIMD
INST(asimd_VNEG, "VNEG", "111100111D11zz01dddd0F111QM0mmmm") // ASIMD
INST(asimd_VSWP, "VSWP", "111100111D110010dddd00000QM0mmmm") // ASIMD
//INST(asimd_VTRN, "VTRN", "111100111-11--10----00001x-0----") // ASIMD
//INST(asimd_VUZP, "VUZP", "111100111-11--10----00010x-0----") // ASIMD

26
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
View file

@ -9,6 +9,32 @@
namespace Dynarmic::A32 {
bool ArmTranslatorVisitor::asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
if (sz == 0b11 || (F && sz != 0b10)) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto result = [this, F, m, sz] {
const auto reg_m = ir.GetVector(m);
if (F) {
return ir.FPVectorNeg(32, reg_m);
}
const size_t esize = 8U << sz;
return ir.VectorSub(esize, ir.ZeroVector(), reg_m);
}();
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -449,6 +449,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous
bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm);
// Advanced SIMD load/store structures