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thumb32: Implement RSB (immediate)

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This commit is contained in:
MerryMage 2021-02-28 21:48:51 +00:00
parent 8d33de2dcc
commit 170ab30b8e
3 changed files with 20 additions and 1 deletions
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2
src/frontend/A32/decoder/thumb32.inc
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@ -68,7 +68,7 @@ INST(thumb32_ADC_imm, "ADC (imm)", "11110v01010Snnnn0vvvdd
INST(thumb32_SBC_imm, "SBC (imm)", "11110v01011Snnnn0vvvddddvvvvvvvv")
INST(thumb32_CMP_imm, "CMP (imm)", "11110v011011nnnn0vvv1111vvvvvvvv")
INST(thumb32_SUB_imm_1, "SUB (imm)", "11110v01101Snnnn0vvvddddvvvvvvvv")
//INST(thumb32_RSB_imm, "RSB (imm)", "11110-01110-----0---------------")
INST(thumb32_RSB_imm, "RSB (imm)", "11110v01110Snnnn0vvvddddvvvvvvvv")
// Data Processing (Plain Binary Immediate)
//INST(thumb32_ADR, "ADR", "11110-10000011110---------------")

18
src/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp
View file

@ -262,4 +262,22 @@ bool ThumbTranslatorVisitor::thumb32_SUB_imm_1(Imm<1> i, bool S, Reg n, Imm<3> i
return true;
}
bool ThumbTranslatorVisitor::thumb32_RSB_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC || n == Reg::PC) {
return UnpredictableInstruction();
}
const auto imm32 = ThumbExpandImm(i, imm3, imm8);
const auto result = ir.SubWithCarry(ir.Imm32(imm32), ir.GetRegister(n), ir.Imm1(1));
ir.SetRegister(d, result.result);
if (S) {
ir.SetNFlag(ir.MostSignificantBit(result.result));
ir.SetZFlag(ir.IsZero(result.result));
ir.SetCFlag(result.carry);
ir.SetVFlag(result.overflow);
}
return true;
}
} // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_thumb.h
View file

@ -164,6 +164,7 @@ struct ThumbTranslatorVisitor final {
bool thumb32_SBC_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_CMP_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm8);
bool thumb32_SUB_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_RSB_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
// thumb32 data processing (plain binary immediate) instructions.
bool thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);