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A64: Implement SQDMULH's scalar variant

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Lioncash 2018-09-05 23:36:52 -04:00 committed by MerryMage
parent 7ebfd0f31c
commit 1a69a61cb4
2 changed files with 18 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -454,7 +454,7 @@ INST(SRSHL_1, "SRSHL", "01011
//INST(SQRSHL_1, "SQRSHL", "01011110zz1mmmmm010111nnnnnddddd")
INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd")
INST(CMTST_1, "CMTST", "01011110zz1mmmmm100011nnnnnddddd")
//INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd")
INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd")
INST(UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd")
INST(UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd")
INST(CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd")

17
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
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@ -137,6 +137,23 @@ bool TranslatorVisitor::SQADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SQDMULH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b00 || size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const IR::UAny operand1 = V_scalar(esize, Vn);
const IR::UAny operand2 = V_scalar(esize, Vm);
const auto result = ir.SignedSaturatedDoublingMultiplyReturnHigh(operand1, operand2);
ir.OrQC(result.overflow);
V_scalar(esize, Vd, result.result);
return true;
}
bool TranslatorVisitor::SQSUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = 8 << size.ZeroExtend<size_t>();