A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)

There wasn't a clean way to seperate these instructions out.

src/CMakeLists.txt

@@ -93,6 +93,7 @@ add_library(dynarmic
     frontend/A64/translate/impl/move_wide.cpp
     frontend/A64/translate/impl/simd_aes.cpp
     frontend/A64/translate/impl/simd_copy.cpp
+    frontend/A64/translate/impl/simd_modified_immediate.cpp
     frontend/A64/translate/impl/simd_scalar_three_same.cpp
     frontend/A64/translate/impl/simd_three_same.cpp
     frontend/A64/translate/impl/system.cpp

src/frontend/A64/decoder/a64.inc

@@ -798,12 +798,8 @@ INST(EOR_asimd,              "EOR (vector)",                              "0Q101
 //INST(BIF,                    "BIF",                                       "0Q101110111mmmmm000111nnnnnddddd")
 
 // Data Processing - FP and SIMD - SIMD modified immediate
-//INST(MOVI,                   "MOVI",                                      "0Qo0111100000abcmmmm01defghddddd")
+INST(MOVI,                   "MOVI, MVNI, ORR, BIC (vector, immediate)",  "0Qo0111100000abcmmmm01defghddddd")
-//INST(ORR_asimd_imm,          "ORR (vector, immediate)",                   "0Q00111100000abc---101defghddddd")
+//INST(FMOV_2,                 "FMOV (vector, immediate)",                  "0Q00111100000abc111111defghddddd")
-//INST(FMOV_1,                 "FMOV (vector, immediate)",                  "0Q00111100000abc111111defghddddd")
-//INST(FMOV_2,                 "FMOV (vector, immediate)",                  "0Qo0111100000abc111101defghddddd")
-//INST(MVNI,                   "MVNI",                                      "0Q10111100000abcmmmm01defghddddd")
-//INST(BIC_imm,                "BIC (vector, immediate)",                   "0Q10111100000abc---101defghddddd")
 
 // Data Processing - FP and SIMD - SIMD Shfit by immediate
 //INST(SHRN,                   "SHRN, SHRN2",                               "0Q0011110IIIIiii100001nnnnnddddd")

src/frontend/A64/translate/impl/impl.h

@@ -871,12 +871,8 @@ struct TranslatorVisitor final {
     bool BIF(bool Q, Vec Vm, Vec Vn, Vec Vd);
 
     // Data Processing - FP and SIMD - SIMD modified immediate
-    bool MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
+    bool MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd);
-    bool ORR_asimd_imm(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
+    bool FMOV_2(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
-    bool FMOV_1(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
-    bool FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
-    bool MVNI(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
-    bool BIC_imm(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
 
     // Data Processing - FP and SIMD - SIMD Shfit by immediate
     bool SHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);

src/frontend/A64/translate/impl/simd_modified_immediate.cpp

@@ -0,0 +1,79 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2018 MerryMage
+ * This software may be used and distributed according to the terms of the GNU
+ * General Public License version 2 or any later version.
+ */
+
+#include "common/bit_util.h"
+#include "frontend/A64/translate/impl/impl.h"
+
+namespace Dynarmic::A64 {
+
+bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd) {
+    const size_t datasize = Q ? 128 : 64;
+
+    // MOVI
+    // also FMOV (vector, immediate) when cmode == 0b1111
+    const auto movi = [&]{
+        u64 imm64 = AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h));
+        const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast64(ir.Imm64(imm64));
+        V(128, Vd, imm);
+        return true;
+    };
+
+    // MVNI
+    const auto mvni = [&]{
+        u64 imm64 = ~AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h));
+        const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast64(ir.Imm64(imm64));
+        V(128, Vd, imm);
+        return true;
+    };
+
+    // ORR (vector, immediate)
+    const auto orr = [&]{
+        u64 imm64 = AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h));
+        const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast64(ir.Imm64(imm64));
+        const IR::U128 operand = V(datasize, Vd);
+        const IR::U128 result = ir.VectorOr(operand, imm);
+        V(datasize, Vd, result);
+        return true;
+    };
+
+    // BIC (vector, immediate)
+    const auto bic = [&]{
+        u64 imm64 = ~AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h));
+        const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast64(ir.Imm64(imm64));
+        const IR::U128 operand = V(datasize, Vd);
+        const IR::U128 result = ir.VectorAnd(operand, imm);
+        V(datasize, Vd, result);
+        return true;
+    };
+
+    switch (concatenate(cmode, Imm<1>{op}).ZeroExtend()) {
+    case 0b00000: case 0b00100: case 0b01000: case 0b01100:
+    case 0b10000: case 0b10100:
+    case 0b11000: case 0b11010:
+    case 0b11100: case 0b11101: case 0b11110:
+        return movi();
+    case 0b11111:
+        if (!Q) {
+            return UnallocatedEncoding();
+        }
+        return movi();
+    case 0b00001: case 0b00101: case 0b01001: case 0b01101:
+    case 0b10001: case 0b10101:
+    case 0b11001: case 0b11011:
+        return mvni();
+    case 0b00010: case 0b00110: case 0b01010: case 0b01110:
+    case 0b10010: case 0b10110:
+        return orr();
+    case 0b00011: case 0b00111: case 0b01011: case 0b01111:
+    case 0b10011: case 0b10111:
+        return bic();
+    }
+
+    UNREACHABLE();
+    return true;
+}
+
+} // namespace Dynarmic::A64