Merge pull request #496 from lioncash/thumb-hint
A32: Implement Thumb-1 hint instructions
This commit is contained in:
commit
1c47e638fc
10 changed files with 82 additions and 1 deletions
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@ -26,6 +26,8 @@ enum class Exception {
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UnpredictableInstruction,
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UnpredictableInstruction,
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/// A SEV instruction was executed. The event register of all PEs should be set.
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/// A SEV instruction was executed. The event register of all PEs should be set.
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SendEvent,
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SendEvent,
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/// A SEVL instruction was executed. The event register of the current PE should be set.
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SendEventLocal,
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/// A WFI instruction was executed. You may now enter a low-power state.
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/// A WFI instruction was executed. You may now enter a low-power state.
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WaitForInterrupt,
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WaitForInterrupt,
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/// A WFE instruction was executed. You may now enter a low-power state if the event register is clear.
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/// A WFE instruction was executed. You may now enter a low-power state if the event register is clear.
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@ -34,7 +34,7 @@ enum class Exception {
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WaitForEvent,
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WaitForEvent,
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/// A SEV instruction was executed. The event register of all PEs should be set.
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/// A SEV instruction was executed. The event register of all PEs should be set.
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SendEvent,
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SendEvent,
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/// A SEV instruction was executed. The event register of the current PE should be set.
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/// A SEVL instruction was executed. The event register of the current PE should be set.
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SendEventLocal,
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SendEventLocal,
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/// A YIELD instruction was executed.
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/// A YIELD instruction was executed.
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Yield,
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Yield,
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@ -97,6 +97,7 @@ INST(arm_UXTAH, "UXTAH", "cccc01101111nnnnddddrr000111mmmm
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INST(arm_PLD_imm, "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii") // v5E for PLD; v7 for PLDW
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INST(arm_PLD_imm, "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii") // v5E for PLD; v7 for PLDW
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INST(arm_PLD_reg, "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm") // v5E for PLD; v7 for PLDW
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INST(arm_PLD_reg, "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm") // v5E for PLD; v7 for PLDW
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INST(arm_SEV, "SEV", "----0011001000001111000000000100") // v6K
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INST(arm_SEV, "SEV", "----0011001000001111000000000100") // v6K
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INST(arm_SEVL, "SEVL", "----0011001000001111000000000101") // v8
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INST(arm_WFE, "WFE", "----0011001000001111000000000010") // v6K
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INST(arm_WFE, "WFE", "----0011001000001111000000000010") // v6K
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INST(arm_WFI, "WFI", "----0011001000001111000000000011") // v6K
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INST(arm_WFI, "WFI", "----0011001000001111000000000011") // v6K
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INST(arm_YIELD, "YIELD", "----0011001000001111000000000001") // v6K
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INST(arm_YIELD, "YIELD", "----0011001000001111000000000001") // v6K
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@ -87,6 +87,14 @@ std::optional<std::reference_wrapper<const Thumb16Matcher<V>>> DecodeThumb16(u16
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INST(&V::thumb16_ADD_sp_t2, "ADD (SP plus imm, T2)", "101100000vvvvvvv"), // v4T
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INST(&V::thumb16_ADD_sp_t2, "ADD (SP plus imm, T2)", "101100000vvvvvvv"), // v4T
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INST(&V::thumb16_SUB_sp, "SUB (SP minus imm)", "101100001vvvvvvv"), // v4T
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INST(&V::thumb16_SUB_sp, "SUB (SP minus imm)", "101100001vvvvvvv"), // v4T
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// Hint instructions
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INST(&V::thumb16_NOP, "NOP", "1011111100000000"), // v6T2
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INST(&V::thumb16_SEV, "SEV", "1011111101000000"), // v7
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INST(&V::thumb16_SEVL, "SEVL", "1011111101010000"), // v8
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INST(&V::thumb16_WFE, "WFE", "1011111100100000"), // v7
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INST(&V::thumb16_WFI, "WFI", "1011111100110000"), // v7
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INST(&V::thumb16_YIELD, "YIELD", "1011111100010000"), // v7
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// Miscellaneous 16-bit instructions
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// Miscellaneous 16-bit instructions
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INST(&V::thumb16_SXTH, "SXTH", "1011001000mmmddd"), // v6
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INST(&V::thumb16_SXTH, "SXTH", "1011001000mmmddd"), // v6
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INST(&V::thumb16_SXTB, "SXTB", "1011001001mmmddd"), // v6
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INST(&V::thumb16_SXTB, "SXTB", "1011001001mmmddd"), // v6
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@ -127,6 +127,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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//INST(&V::thumb32_WFE, "WFE", "111100111010----10-0-00000000010"),
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//INST(&V::thumb32_WFE, "WFE", "111100111010----10-0-00000000010"),
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//INST(&V::thumb32_WFI, "WFI", "111100111010----10-0-00000000011"),
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//INST(&V::thumb32_WFI, "WFI", "111100111010----10-0-00000000011"),
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//INST(&V::thumb32_SEV, "SEV", "111100111010----10-0-00000000100"),
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//INST(&V::thumb32_SEV, "SEV", "111100111010----10-0-00000000100"),
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//INST(&V::thumb32_SEVL, "SEVL", "111100111010----10-0-00000000101"),
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//INST(&V::thumb32_DBG, "DBG", "111100111010----10-0-0001111----"),
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//INST(&V::thumb32_DBG, "DBG", "111100111010----10-0-0001111----"),
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//INST(&V::thumb32_CPS, "CPS", "111100111010----10-0------------"),
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//INST(&V::thumb32_CPS, "CPS", "111100111010----10-0------------"),
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@ -451,6 +451,9 @@ public:
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std::string arm_SEV() {
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std::string arm_SEV() {
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return "sev";
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return "sev";
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}
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}
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std::string arm_SEVL() {
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return "sevl";
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}
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std::string arm_WFE() {
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std::string arm_WFE() {
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return "wfe";
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return "wfe";
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}
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}
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@ -246,6 +246,30 @@ public:
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return fmt::format("sub sp, sp, #{}", imm32);
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return fmt::format("sub sp, sp, #{}", imm32);
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}
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}
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std::string thumb16_NOP() {
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return "nop";
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}
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std::string thumb16_SEV() {
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return "sev";
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}
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std::string thumb16_SEVL() {
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return "sevl";
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}
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std::string thumb16_WFE() {
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return "wfe";
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}
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std::string thumb16_WFI() {
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return "wfi";
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}
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std::string thumb16_YIELD() {
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return "yield";
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}
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std::string thumb16_SXTH(Reg m, Reg d) {
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std::string thumb16_SXTH(Reg m, Reg d) {
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return fmt::format("sxth {}, {}", d, m);
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return fmt::format("sxth {}, {}", d, m);
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}
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}
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@ -33,6 +33,10 @@ bool ArmTranslatorVisitor::arm_SEV() {
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return RaiseException(Exception::SendEvent);
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return RaiseException(Exception::SendEvent);
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}
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}
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bool ArmTranslatorVisitor::arm_SEVL() {
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return RaiseException(Exception::SendEventLocal);
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}
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bool ArmTranslatorVisitor::arm_WFE() {
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bool ArmTranslatorVisitor::arm_WFE() {
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return RaiseException(Exception::WaitForEvent);
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return RaiseException(Exception::WaitForEvent);
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}
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}
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@ -167,6 +167,7 @@ struct ArmTranslatorVisitor final {
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bool arm_PLD_imm(bool add, bool R, Reg n, Imm<12> imm12);
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bool arm_PLD_imm(bool add, bool R, Reg n, Imm<12> imm12);
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bool arm_PLD_reg(bool add, bool R, Reg n, Imm<5> imm5, ShiftType shift, Reg m);
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bool arm_PLD_reg(bool add, bool R, Reg n, Imm<5> imm5, ShiftType shift, Reg m);
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bool arm_SEV();
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bool arm_SEV();
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bool arm_SEVL();
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bool arm_WFE();
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bool arm_WFE();
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bool arm_WFI();
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bool arm_WFI();
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bool arm_YIELD();
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bool arm_YIELD();
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@ -41,6 +41,13 @@ struct ThumbTranslatorVisitor final {
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return false;
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return false;
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}
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}
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bool RaiseException(Exception exception) {
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ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 2));
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ir.ExceptionRaised(exception);
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ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
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return false;
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}
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// LSLS <Rd>, <Rm>, #<imm5>
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// LSLS <Rd>, <Rm>, #<imm5>
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bool thumb16_LSL_imm(Imm<5> imm5, Reg m, Reg d) {
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bool thumb16_LSL_imm(Imm<5> imm5, Reg m, Reg d) {
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const u8 shift_n = imm5.ZeroExtend<u8>();
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const u8 shift_n = imm5.ZeroExtend<u8>();
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@ -667,6 +674,36 @@ struct ThumbTranslatorVisitor final {
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return true;
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return true;
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}
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}
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// NOP<c>
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bool thumb16_NOP() {
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return true;
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}
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// SEV<c>
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bool thumb16_SEV() {
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return RaiseException(Exception::SendEvent);
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}
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// SEVL<c>
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bool thumb16_SEVL() {
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return RaiseException(Exception::SendEventLocal);
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}
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// WFE<c>
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bool thumb16_WFE() {
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return RaiseException(Exception::WaitForEvent);
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}
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// WFI<c>
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bool thumb16_WFI() {
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return RaiseException(Exception::WaitForInterrupt);
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}
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// YIELD<c>
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bool thumb16_YIELD() {
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return RaiseException(Exception::Yield);
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}
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// SXTH <Rd>, <Rm>
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// SXTH <Rd>, <Rm>
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// Rd cannot encode R15.
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// Rd cannot encode R15.
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bool thumb16_SXTH(Reg m, Reg d) {
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bool thumb16_SXTH(Reg m, Reg d) {
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