Merge pull request #496 from lioncash/thumb-hint

A32: Implement Thumb-1 hint instructions
This commit is contained in:
Merry 2019-05-03 21:22:37 +01:00 committed by MerryMage
commit 1c47e638fc
10 changed files with 82 additions and 1 deletions

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@ -26,6 +26,8 @@ enum class Exception {
UnpredictableInstruction, UnpredictableInstruction,
/// A SEV instruction was executed. The event register of all PEs should be set. /// A SEV instruction was executed. The event register of all PEs should be set.
SendEvent, SendEvent,
/// A SEVL instruction was executed. The event register of the current PE should be set.
SendEventLocal,
/// A WFI instruction was executed. You may now enter a low-power state. /// A WFI instruction was executed. You may now enter a low-power state.
WaitForInterrupt, WaitForInterrupt,
/// A WFE instruction was executed. You may now enter a low-power state if the event register is clear. /// A WFE instruction was executed. You may now enter a low-power state if the event register is clear.

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@ -34,7 +34,7 @@ enum class Exception {
WaitForEvent, WaitForEvent,
/// A SEV instruction was executed. The event register of all PEs should be set. /// A SEV instruction was executed. The event register of all PEs should be set.
SendEvent, SendEvent,
/// A SEV instruction was executed. The event register of the current PE should be set. /// A SEVL instruction was executed. The event register of the current PE should be set.
SendEventLocal, SendEventLocal,
/// A YIELD instruction was executed. /// A YIELD instruction was executed.
Yield, Yield,

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@ -97,6 +97,7 @@ INST(arm_UXTAH, "UXTAH", "cccc01101111nnnnddddrr000111mmmm
INST(arm_PLD_imm, "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii") // v5E for PLD; v7 for PLDW INST(arm_PLD_imm, "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii") // v5E for PLD; v7 for PLDW
INST(arm_PLD_reg, "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm") // v5E for PLD; v7 for PLDW INST(arm_PLD_reg, "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm") // v5E for PLD; v7 for PLDW
INST(arm_SEV, "SEV", "----0011001000001111000000000100") // v6K INST(arm_SEV, "SEV", "----0011001000001111000000000100") // v6K
INST(arm_SEVL, "SEVL", "----0011001000001111000000000101") // v8
INST(arm_WFE, "WFE", "----0011001000001111000000000010") // v6K INST(arm_WFE, "WFE", "----0011001000001111000000000010") // v6K
INST(arm_WFI, "WFI", "----0011001000001111000000000011") // v6K INST(arm_WFI, "WFI", "----0011001000001111000000000011") // v6K
INST(arm_YIELD, "YIELD", "----0011001000001111000000000001") // v6K INST(arm_YIELD, "YIELD", "----0011001000001111000000000001") // v6K

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@ -87,6 +87,14 @@ std::optional<std::reference_wrapper<const Thumb16Matcher<V>>> DecodeThumb16(u16
INST(&V::thumb16_ADD_sp_t2, "ADD (SP plus imm, T2)", "101100000vvvvvvv"), // v4T INST(&V::thumb16_ADD_sp_t2, "ADD (SP plus imm, T2)", "101100000vvvvvvv"), // v4T
INST(&V::thumb16_SUB_sp, "SUB (SP minus imm)", "101100001vvvvvvv"), // v4T INST(&V::thumb16_SUB_sp, "SUB (SP minus imm)", "101100001vvvvvvv"), // v4T
// Hint instructions
INST(&V::thumb16_NOP, "NOP", "1011111100000000"), // v6T2
INST(&V::thumb16_SEV, "SEV", "1011111101000000"), // v7
INST(&V::thumb16_SEVL, "SEVL", "1011111101010000"), // v8
INST(&V::thumb16_WFE, "WFE", "1011111100100000"), // v7
INST(&V::thumb16_WFI, "WFI", "1011111100110000"), // v7
INST(&V::thumb16_YIELD, "YIELD", "1011111100010000"), // v7
// Miscellaneous 16-bit instructions // Miscellaneous 16-bit instructions
INST(&V::thumb16_SXTH, "SXTH", "1011001000mmmddd"), // v6 INST(&V::thumb16_SXTH, "SXTH", "1011001000mmmddd"), // v6
INST(&V::thumb16_SXTB, "SXTB", "1011001001mmmddd"), // v6 INST(&V::thumb16_SXTB, "SXTB", "1011001001mmmddd"), // v6

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@ -127,6 +127,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
//INST(&V::thumb32_WFE, "WFE", "111100111010----10-0-00000000010"), //INST(&V::thumb32_WFE, "WFE", "111100111010----10-0-00000000010"),
//INST(&V::thumb32_WFI, "WFI", "111100111010----10-0-00000000011"), //INST(&V::thumb32_WFI, "WFI", "111100111010----10-0-00000000011"),
//INST(&V::thumb32_SEV, "SEV", "111100111010----10-0-00000000100"), //INST(&V::thumb32_SEV, "SEV", "111100111010----10-0-00000000100"),
//INST(&V::thumb32_SEVL, "SEVL", "111100111010----10-0-00000000101"),
//INST(&V::thumb32_DBG, "DBG", "111100111010----10-0-0001111----"), //INST(&V::thumb32_DBG, "DBG", "111100111010----10-0-0001111----"),
//INST(&V::thumb32_CPS, "CPS", "111100111010----10-0------------"), //INST(&V::thumb32_CPS, "CPS", "111100111010----10-0------------"),

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@ -451,6 +451,9 @@ public:
std::string arm_SEV() { std::string arm_SEV() {
return "sev"; return "sev";
} }
std::string arm_SEVL() {
return "sevl";
}
std::string arm_WFE() { std::string arm_WFE() {
return "wfe"; return "wfe";
} }

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@ -246,6 +246,30 @@ public:
return fmt::format("sub sp, sp, #{}", imm32); return fmt::format("sub sp, sp, #{}", imm32);
} }
std::string thumb16_NOP() {
return "nop";
}
std::string thumb16_SEV() {
return "sev";
}
std::string thumb16_SEVL() {
return "sevl";
}
std::string thumb16_WFE() {
return "wfe";
}
std::string thumb16_WFI() {
return "wfi";
}
std::string thumb16_YIELD() {
return "yield";
}
std::string thumb16_SXTH(Reg m, Reg d) { std::string thumb16_SXTH(Reg m, Reg d) {
return fmt::format("sxth {}, {}", d, m); return fmt::format("sxth {}, {}", d, m);
} }

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@ -33,6 +33,10 @@ bool ArmTranslatorVisitor::arm_SEV() {
return RaiseException(Exception::SendEvent); return RaiseException(Exception::SendEvent);
} }
bool ArmTranslatorVisitor::arm_SEVL() {
return RaiseException(Exception::SendEventLocal);
}
bool ArmTranslatorVisitor::arm_WFE() { bool ArmTranslatorVisitor::arm_WFE() {
return RaiseException(Exception::WaitForEvent); return RaiseException(Exception::WaitForEvent);
} }

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@ -167,6 +167,7 @@ struct ArmTranslatorVisitor final {
bool arm_PLD_imm(bool add, bool R, Reg n, Imm<12> imm12); bool arm_PLD_imm(bool add, bool R, Reg n, Imm<12> imm12);
bool arm_PLD_reg(bool add, bool R, Reg n, Imm<5> imm5, ShiftType shift, Reg m); bool arm_PLD_reg(bool add, bool R, Reg n, Imm<5> imm5, ShiftType shift, Reg m);
bool arm_SEV(); bool arm_SEV();
bool arm_SEVL();
bool arm_WFE(); bool arm_WFE();
bool arm_WFI(); bool arm_WFI();
bool arm_YIELD(); bool arm_YIELD();

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@ -41,6 +41,13 @@ struct ThumbTranslatorVisitor final {
return false; return false;
} }
bool RaiseException(Exception exception) {
ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 2));
ir.ExceptionRaised(exception);
ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
return false;
}
// LSLS <Rd>, <Rm>, #<imm5> // LSLS <Rd>, <Rm>, #<imm5>
bool thumb16_LSL_imm(Imm<5> imm5, Reg m, Reg d) { bool thumb16_LSL_imm(Imm<5> imm5, Reg m, Reg d) {
const u8 shift_n = imm5.ZeroExtend<u8>(); const u8 shift_n = imm5.ZeroExtend<u8>();
@ -667,6 +674,36 @@ struct ThumbTranslatorVisitor final {
return true; return true;
} }
// NOP<c>
bool thumb16_NOP() {
return true;
}
// SEV<c>
bool thumb16_SEV() {
return RaiseException(Exception::SendEvent);
}
// SEVL<c>
bool thumb16_SEVL() {
return RaiseException(Exception::SendEventLocal);
}
// WFE<c>
bool thumb16_WFE() {
return RaiseException(Exception::WaitForEvent);
}
// WFI<c>
bool thumb16_WFI() {
return RaiseException(Exception::WaitForInterrupt);
}
// YIELD<c>
bool thumb16_YIELD() {
return RaiseException(Exception::Yield);
}
// SXTH <Rd>, <Rm> // SXTH <Rd>, <Rm>
// Rd cannot encode R15. // Rd cannot encode R15.
bool thumb16_SXTH(Reg m, Reg d) { bool thumb16_SXTH(Reg m, Reg d) {