A64: Implement SIMD instruction SHL
This commit is contained in:
MerryMage
parent
f6247125c0
commit
1d0cd95b23
5 changed files with 100 additions and 50 deletions
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@ -97,6 +97,7 @@ add_library(dynarmic
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frontend/A64/translate/impl/simd_modified_immediate.cpp
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frontend/A64/translate/impl/simd_permute.cpp
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frontend/A64/translate/impl/simd_scalar_three_same.cpp
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frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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frontend/A64/translate/impl/simd_three_same.cpp
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frontend/A64/translate/impl/system.cpp
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frontend/A64/translate/translate.cpp
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@ -511,53 +511,29 @@ INST(SUB_1, "SUB (vector)", "01111
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// Data Processing - FP and SIMD - SIMD Scalar shift by immediate
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//INST(SSHR_1, "SSHR", "010111110IIIIiii000001nnnnnddddd")
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//INST(SSHR_2, "SSHR", "0Q0011110IIIIiii000001nnnnnddddd")
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//INST(SSRA_1, "SSRA", "010111110IIIIiii000101nnnnnddddd")
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//INST(SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd")
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//INST(SRSHR_1, "SRSHR", "010111110IIIIiii001001nnnnnddddd")
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//INST(SRSHR_2, "SRSHR", "0Q0011110IIIIiii001001nnnnnddddd")
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//INST(SRSRA_1, "SRSRA", "010111110IIIIiii001101nnnnnddddd")
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//INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd")
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//INST(SHL_1, "SHL", "010111110IIIIiii010101nnnnnddddd")
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//INST(SHL_2, "SHL", "0Q0011110IIIIiii010101nnnnnddddd")
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//INST(SQSHL_imm_1, "SQSHL (immediate)", "010111110IIIIiii011101nnnnnddddd")
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//INST(SQSHL_imm_2, "SQSHL (immediate)", "0Q0011110IIIIiii011101nnnnnddddd")
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//INST(SQSHRN_1, "SQSHRN, SQSHRN2", "010111110IIIIiii100101nnnnnddddd")
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//INST(SQSHRN_2, "SQSHRN, SQSHRN2", "0Q0011110IIIIiii100101nnnnnddddd")
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//INST(SQRSHRN_1, "SQRSHRN, SQRSHRN2", "010111110IIIIiii100111nnnnnddddd")
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//INST(SQRSHRN_2, "SQRSHRN, SQRSHRN2", "0Q0011110IIIIiii100111nnnnnddddd")
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//INST(SCVTF_fix_1, "SCVTF (vector, fixed-point)", "010111110IIIIiii111001nnnnnddddd")
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//INST(SCVTF_fix_2, "SCVTF (vector, fixed-point)", "0Q0011110IIIIiii111001nnnnnddddd")
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//INST(FCVTZS_fix_1, "FCVTZS (vector, fixed-point)", "010111110IIIIiii111111nnnnnddddd")
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//INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd")
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//INST(USHR_1, "USHR", "011111110IIIIiii000001nnnnnddddd")
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//INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd")
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//INST(USRA_1, "USRA", "011111110IIIIiii000101nnnnnddddd")
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//INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
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//INST(URSHR_1, "URSHR", "011111110IIIIiii001001nnnnnddddd")
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//INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
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//INST(URSRA_1, "URSRA", "011111110IIIIiii001101nnnnnddddd")
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//INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd")
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//INST(SRI_1, "SRI", "011111110IIIIiii010001nnnnnddddd")
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//INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd")
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//INST(SLI_1, "SLI", "011111110IIIIiii010101nnnnnddddd")
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//INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd")
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//INST(SQSHLU_1, "SQSHLU", "011111110IIIIiii011001nnnnnddddd")
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//INST(SQSHLU_2, "SQSHLU", "0Q1011110IIIIiii011001nnnnnddddd")
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//INST(UQSHL_imm_1, "UQSHL (immediate)", "011111110IIIIiii011101nnnnnddddd")
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//INST(UQSHL_imm_2, "UQSHL (immediate)", "0Q1011110IIIIiii011101nnnnnddddd")
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//INST(SQSHRUN_1, "SQSHRUN, SQSHRUN2", "011111110IIIIiii100001nnnnnddddd")
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//INST(SQSHRUN_2, "SQSHRUN, SQSHRUN2", "0Q1011110IIIIiii100001nnnnnddddd")
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//INST(SQRSHRUN_1, "SQRSHRUN, SQRSHRUN2", "011111110IIIIiii100011nnnnnddddd")
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//INST(SQRSHRUN_2, "SQRSHRUN, SQRSHRUN2", "0Q1011110IIIIiii100011nnnnnddddd")
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//INST(UQSHRN_1, "UQSHRN, UQSHRN2", "011111110IIIIiii100101nnnnnddddd")
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//INST(UQSHRN_2, "UQSHRN, UQSHRN2", "0Q1011110IIIIiii100101nnnnnddddd")
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//INST(UQRSHRN_1, "UQRSHRN, UQRSHRN2", "011111110IIIIiii100111nnnnnddddd")
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//INST(UQRSHRN_2, "UQRSHRN, UQRSHRN2", "0Q1011110IIIIiii100111nnnnnddddd")
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//INST(UCVTF_fix_1, "UCVTF (vector, fixed-point)", "011111110IIIIiii111001nnnnnddddd")
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//INST(UCVTF_fix_2, "UCVTF (vector, fixed-point)", "0Q1011110IIIIiii111001nnnnnddddd")
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//INST(FCVTZU_fix_1, "FCVTZU (vector, fixed-point)", "011111110IIIIiii111111nnnnnddddd")
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//INST(FCVTZU_fix_2, "FCVTZU (vector, fixed-point)", "0Q1011110IIIIiii111111nnnnnddddd")
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// Data Processing - FP and SIMD - SIMD Scalar x indexed element
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//INST(SQDMLAL_elt_1, "SQDMLAL, SQDMLAL2 (by element)", "01011111zzLMmmmm0011H0nnnnnddddd")
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@ -801,11 +777,35 @@ INST(BIF, "BIF", "0Q101
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INST(MOVI, "MOVI, MVNI, ORR, BIC (vector, immediate)", "0Qo0111100000abcmmmm01defghddddd")
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//INST(FMOV_2, "FMOV (vector, immediate)", "0Q00111100000abc111111defghddddd")
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// Data Processing - FP and SIMD - SIMD Shfit by immediate
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// Data Processing - FP and SIMD - SIMD Shift by immediate
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//INST(SSHR_2, "SSHR", "0Q0011110IIIIiii000001nnnnnddddd")
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//INST(SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd")
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//INST(SRSHR_2, "SRSHR", "0Q0011110IIIIiii001001nnnnnddddd")
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//INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd")
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INST(SHL_2, "SHL", "0Q0011110IIIIiii010101nnnnnddddd")
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//INST(SQSHL_imm_2, "SQSHL (immediate)", "0Q0011110IIIIiii011101nnnnnddddd")
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//INST(SHRN, "SHRN, SHRN2", "0Q0011110IIIIiii100001nnnnnddddd")
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//INST(RSHRN, "RSHRN, RSHRN2", "0Q0011110IIIIiii100011nnnnnddddd")
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//INST(SQSHRN_2, "SQSHRN, SQSHRN2", "0Q0011110IIIIiii100101nnnnnddddd")
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//INST(SQRSHRN_2, "SQRSHRN, SQRSHRN2", "0Q0011110IIIIiii100111nnnnnddddd")
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//INST(SSHLL, "SSHLL, SSHLL2", "0Q0011110IIIIiii101001nnnnnddddd")
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//INST(SCVTF_fix_2, "SCVTF (vector, fixed-point)", "0Q0011110IIIIiii111001nnnnnddddd")
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//INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd")
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//INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd")
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//INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
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//INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
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//INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd")
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//INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd")
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//INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd")
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//INST(SQSHLU_2, "SQSHLU", "0Q1011110IIIIiii011001nnnnnddddd")
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//INST(UQSHL_imm_2, "UQSHL (immediate)", "0Q1011110IIIIiii011101nnnnnddddd")
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//INST(SQSHRUN_2, "SQSHRUN, SQSHRUN2", "0Q1011110IIIIiii100001nnnnnddddd")
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//INST(SQRSHRUN_2, "SQRSHRUN, SQRSHRUN2", "0Q1011110IIIIiii100011nnnnnddddd")
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//INST(UQSHRN_2, "UQSHRN, UQSHRN2", "0Q1011110IIIIiii100101nnnnnddddd")
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//INST(UQRSHRN_2, "UQRSHRN, UQRSHRN2", "0Q1011110IIIIiii100111nnnnnddddd")
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//INST(USHLL, "USHLL, USHLL2", "0Q1011110IIIIiii101001nnnnnddddd")
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//INST(UCVTF_fix_2, "UCVTF (vector, fixed-point)", "0Q1011110IIIIiii111001nnnnnddddd")
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//INST(FCVTZU_fix_2, "FCVTZU (vector, fixed-point)", "0Q1011110IIIIiii111111nnnnnddddd")
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// Data Processing - FP and SIMD - SIMD x indexed element
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//INST(SMLAL_elt, "SMLAL, SMLAL2 (by element)", "0Q001111zzLMmmmm0010H0nnnnnddddd")
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@ -21,6 +21,11 @@ bool TranslatorVisitor::UnpredictableInstruction() {
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return false;
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}
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bool TranslatorVisitor::DecodeError() {
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// TODO: This is an internal error.
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return UnallocatedEncoding();
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}
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bool TranslatorVisitor::ReservedValue() {
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ir.ExceptionRaised(Exception::ReservedValue);
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ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
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@ -32,6 +32,7 @@ struct TranslatorVisitor final {
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bool InterpretThisInstruction();
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bool UnpredictableInstruction();
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bool DecodeError();
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bool ReservedValue();
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bool UnallocatedEncoding();
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@ -609,53 +610,29 @@ struct TranslatorVisitor final {
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// Data Processing - FP and SIMD - SIMD Scalar shift by immediate
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bool SSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SHL_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHL_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQRSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SCVTF_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool FCVTZS_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool FCVTZS_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool USHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool USRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool USRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool URSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool URSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool URSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SLI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHLU_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHLU_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool UQSHL_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool UQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHRUN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQRSHRUN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQRSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool UQSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool UQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool UQRSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool UQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool UCVTF_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool UCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool FCVTZU_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool FCVTZU_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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// Data Processing - FP and SIMD - SIMD Scalar x indexed element
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bool SQDMLAL_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
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@ -874,11 +851,35 @@ struct TranslatorVisitor final {
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bool MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd);
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bool FMOV_2(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
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// Data Processing - FP and SIMD - SIMD Shfit by immediate
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// Data Processing - FP and SIMD - SIMD Shift by immediate
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bool SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Reg Rn, Vec Vd);
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bool SCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool FCVTZS_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool USRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool URSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHLU_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool UQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool SQSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool SQRSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool UQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool UQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
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bool USHLL(bool Q, Imm<4> immh, Imm<3> immb, Reg Rn, Vec Vd);
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bool UCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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bool FCVTZU_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
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// Data Processing - FP and SIMD - SIMD x indexed element
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bool SMLAL_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
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43
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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43
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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@ -0,0 +1,43 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "common/bit_util.h"
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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||||
return DecodeError();
|
||||
}
|
||||
if (immh.Bit<3>() && !Q) {
|
||||
return ReservedValue();
|
||||
}
|
||||
const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
|
||||
const size_t datasize = Q ? 128 : 64;
|
||||
|
||||
const u8 shift_amount = concatenate(immh, immb).ZeroExtend<u8>() - static_cast<u8>(esize);
|
||||
|
||||
const IR::U128 operand = V(datasize, Vn);
|
||||
const IR::U128 result = [&]{
|
||||
switch (esize) {
|
||||
case 8:
|
||||
return ir.VectorLogicalShiftLeft8(operand, shift_amount);
|
||||
case 16:
|
||||
return ir.VectorLogicalShiftLeft16(operand, shift_amount);
|
||||
case 32:
|
||||
return ir.VectorLogicalShiftLeft32(operand, shift_amount);
|
||||
case 64:
|
||||
default:
|
||||
return ir.VectorLogicalShiftLeft64(operand, shift_amount);
|
||||
}
|
||||
}();
|
||||
|
||||
V(datasize, Vd, result);
|
||||
return true;
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::A64
|
||||
Loading…
Reference in a new issue