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A32: Implement ASIMD VMAX/VMIN (integer)

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This commit is contained in:
Lioncash 2020-06-20 14:52:10 -04:00 committed by merry
parent 945b757b6c
commit 1ffeeeb6a2
3 changed files with 32 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -18,7 +18,7 @@ INST(asimd_VSHL_reg, "VSHL (register)", "1111001U0Dzznnnndddd010
INST(asimd_VQSHL_reg, "VQSHL (register)", "1111001U0Dzznnnndddd0100NQM1mmmm") // ASIMD INST(asimd_VQSHL_reg, "VQSHL (register)", "1111001U0Dzznnnndddd0100NQM1mmmm") // ASIMD
INST(asimd_VRSHL, "VRSHL", "1111001U0Dzznnnndddd0101NQM0mmmm") // ASIMD INST(asimd_VRSHL, "VRSHL", "1111001U0Dzznnnndddd0101NQM0mmmm") // ASIMD
//INST(asimd_VQRSHL, "VQRSHL", "1111001U0-CC--------0101---1----") // ASIMD //INST(asimd_VQRSHL, "VQRSHL", "1111001U0-CC--------0101---1----") // ASIMD
//INST(asimd_VMAX, "VMAX/VMIN", "1111001U0-CC--------0110---B----") // ASIMD INST(asimd_VMAX, "VMAX/VMIN", "1111001U0Dzznnnnmmmm0110NQMommmm") // ASIMD
//INST(asimd_VABD, "VABD/VABDL", "1111001U0-CC--------0111---0----") // ASIMD //INST(asimd_VABD, "VABD/VABDL", "1111001U0-CC--------0111---0----") // ASIMD
//INST(asimd_VABA, "VABA/ABAL", "1111001U0-CC--------0111---1----") // ASIMD //INST(asimd_VABA, "VABA/ABAL", "1111001U0-CC--------0111---1----") // ASIMD
INST(asimd_VADD_int, "VADD (integer)", "111100100Dzznnnndddd1000NQM0mmmm") // ASIMD INST(asimd_VADD_int, "VADD (integer)", "111100100Dzznnnndddd1000NQM0mmmm") // ASIMD

30
src/frontend/A32/translate/impl/asimd_three_same.cpp
View file

@ -310,6 +310,36 @@ bool ArmTranslatorVisitor::asimd_VRSHL(bool U, bool D, size_t sz, size_t Vn, siz
return true; return true;
} }
bool ArmTranslatorVisitor::asimd_VMAX(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, bool op, size_t Vm) {
if (sz == 0b11) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const auto reg_m = ir.GetVector(m);
const auto reg_n = ir.GetVector(n);
const auto result = [&] {
if (op) {
return U ? ir.VectorMinUnsigned(esize, reg_m, reg_n)
: ir.VectorMinSigned(esize, reg_m, reg_n);
} else {
return U ? ir.VectorMaxUnsigned(esize, reg_m, reg_n)
: ir.VectorMaxSigned(esize, reg_m, reg_n);
}
}();
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { bool ArmTranslatorVisitor::asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction(); return UndefinedInstruction();

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -461,6 +461,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VSHL_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VSHL_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VQSHL_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VQSHL_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VRSHL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VRSHL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMAX(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, bool op, size_t Vm);
bool asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMLA(bool op, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMLA(bool op, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);