A32: Implement ASIMD VRHADD
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946eb03a3b
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205e6c5a56
3 changed files with 24 additions and 1 deletions
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@ -1,7 +1,7 @@
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// Three registers of the same length
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INST(asimd_VHADD, "VHADD", "1111001U0Dzznnnndddd0000NQM0mmmm") // ASIMD
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//INST(asimd_VQADD, "VQADD", "1111001U0-CC--------0000---1----") // ASIMD
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//INST(asimd_VRHADD, "VRHADD", "1111001U0-CC--------0001---0----") // ASIMD
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INST(asimd_VRHADD, "VRHADD", "1111001U0Dzznnnndddd0001NQM0mmmm") // ASIMD
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INST(asimd_VAND_reg, "VAND (register)", "111100100D00nnnndddd0001NQM1mmmm") // ASIMD
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INST(asimd_VBIC_reg, "VBIC (register)", "111100100D01nnnndddd0001NQM1mmmm") // ASIMD
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INST(asimd_VORR_reg, "VORR (register)", "111100100D10nnnndddd0001NQM1mmmm") // ASIMD
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@ -58,6 +58,28 @@ bool ArmTranslatorVisitor::asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, siz
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VRHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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if (sz == 0b11) {
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return UndefinedInstruction();
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}
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const size_t esize = 8 << sz;
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto n = ToVector(Q, Vn, N);
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const IR::U128 reg_n = ir.GetVector(n);
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const IR::U128 reg_m = ir.GetVector(m);
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const IR::U128 result = U ? ir.VectorRoundingHalvingAddUnsigned(esize, reg_n, reg_m) : ir.VectorRoundingHalvingAddSigned(esize, reg_n, reg_m);
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<false>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.VectorAnd(reg_n, reg_m);
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@ -435,6 +435,7 @@ struct ArmTranslatorVisitor final {
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// Advanced SIMD three register variants
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bool asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VRHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VBIC_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VORR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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