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load_store: Implement LDRSB and LDRSH.

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bunnei 2016-08-11 17:18:20 +01:00 committed by MerryMage
parent 0e5593ba62
commit 218980cf69
1 changed files with 52 additions and 4 deletions
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56
src/frontend/translate/translate_arm/load_store.cpp
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@ -225,11 +225,35 @@ bool ArmTranslatorVisitor::arm_LDRHT() {
} }
bool ArmTranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { bool ArmTranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
return InterpretThisInstruction(); if (ConditionPassed(cond)) {
const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b))));
if (d == Reg::PC) {
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
ir.SetRegister(d, data);
}
return true;
} }
bool ArmTranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
return InterpretThisInstruction(); if (ConditionPassed(cond)) {
const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m))));
if (d == Reg::PC) {
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
ir.SetRegister(d, data);
}
return true;
} }
bool ArmTranslatorVisitor::arm_LDRSBT() { bool ArmTranslatorVisitor::arm_LDRSBT() {
@ -237,11 +261,35 @@ bool ArmTranslatorVisitor::arm_LDRSBT() {
} }
bool ArmTranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { bool ArmTranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
return InterpretThisInstruction(); if (ConditionPassed(cond)) {
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b))));
if (d == Reg::PC) {
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
ir.SetRegister(d, data);
}
return true;
} }
bool ArmTranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
return InterpretThisInstruction(); if (ConditionPassed(cond)) {
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m))));
if (d == Reg::PC) {
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
ir.SetRegister(d, data);
}
return true;
} }
bool ArmTranslatorVisitor::arm_LDRSHT() { bool ArmTranslatorVisitor::arm_LDRSHT() {