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ir: Add opcodes for performing scalar integral min/max

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Lioncash 2018-07-29 17:52:27 -04:00 committed by MerryMage
parent 7fdd8b0197
commit 2501bfbfae
4 changed files with 140 additions and 0 deletions
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96
src/backend_x64/emit_x64_data_processing.cpp
View file

@ -1317,4 +1317,100 @@ void EmitX64::EmitCountLeadingZeros64(EmitContext& ctx, IR::Inst* inst) {
}
}
void EmitX64::EmitMaxSigned32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg32 x = ctx.reg_alloc.UseGpr(args[0]).cvt32();
const Xbyak::Reg32 y = ctx.reg_alloc.UseScratchGpr(args[1]).cvt32();
code.cmp(x, y);
code.cmovge(y, x);
ctx.reg_alloc.DefineValue(inst, y);
}
void EmitX64::EmitMaxSigned64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg64 x = ctx.reg_alloc.UseGpr(args[0]);
const Xbyak::Reg64 y = ctx.reg_alloc.UseScratchGpr(args[1]);
code.cmp(x, y);
code.cmovge(y, x);
ctx.reg_alloc.DefineValue(inst, y);
}
void EmitX64::EmitMaxUnsigned32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg32 x = ctx.reg_alloc.UseGpr(args[0]).cvt32();
const Xbyak::Reg32 y = ctx.reg_alloc.UseScratchGpr(args[1]).cvt32();
code.cmp(x, y);
code.cmova(y, x);
ctx.reg_alloc.DefineValue(inst, y);
}
void EmitX64::EmitMaxUnsigned64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg64 x = ctx.reg_alloc.UseGpr(args[0]);
const Xbyak::Reg64 y = ctx.reg_alloc.UseScratchGpr(args[1]);
code.cmp(x, y);
code.cmova(y, x);
ctx.reg_alloc.DefineValue(inst, y);
}
void EmitX64::EmitMinSigned32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg32 x = ctx.reg_alloc.UseGpr(args[0]).cvt32();
const Xbyak::Reg32 y = ctx.reg_alloc.UseScratchGpr(args[1]).cvt32();
code.cmp(x, y);
code.cmovle(y, x);
ctx.reg_alloc.DefineValue(inst, y);
}
void EmitX64::EmitMinSigned64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg64 x = ctx.reg_alloc.UseGpr(args[0]);
const Xbyak::Reg64 y = ctx.reg_alloc.UseScratchGpr(args[1]);
code.cmp(x, y);
code.cmovle(y, x);
ctx.reg_alloc.DefineValue(inst, y);
}
void EmitX64::EmitMinUnsigned32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg32 x = ctx.reg_alloc.UseGpr(args[0]).cvt32();
const Xbyak::Reg32 y = ctx.reg_alloc.UseScratchGpr(args[1]).cvt32();
code.cmp(x, y);
code.cmovb(y, x);
ctx.reg_alloc.DefineValue(inst, y);
}
void EmitX64::EmitMinUnsigned64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg64 x = ctx.reg_alloc.UseGpr(args[0]);
const Xbyak::Reg64 y = ctx.reg_alloc.UseScratchGpr(args[1]);
code.cmp(x, y);
code.cmovb(y, x);
ctx.reg_alloc.DefineValue(inst, y);
}
} // namespace Dynarmic::BackendX64

32
src/frontend/ir/ir_emitter.cpp
View file

@ -449,6 +449,38 @@ U32U64 IREmitter::ExtractRegister(const U32U64& a, const U32U64& b, const U8& ls
return Inst<U64>(Opcode::ExtractRegister64, a, b, lsb);
}
U32U64 IREmitter::MaxSigned(const U32U64& a, const U32U64& b) {
if (a.GetType() == IR::Type::U32) {
return Inst<U32>(Opcode::MaxSigned32, a, b);
}
return Inst<U64>(Opcode::MaxSigned64, a, b);
}
U32U64 IREmitter::MaxUnsigned(const U32U64& a, const U32U64& b) {
if (a.GetType() == IR::Type::U32) {
return Inst<U32>(Opcode::MaxUnsigned32, a, b);
}
return Inst<U64>(Opcode::MaxUnsigned64, a, b);
}
U32U64 IREmitter::MinSigned(const U32U64& a, const U32U64& b) {
if (a.GetType() == IR::Type::U32) {
return Inst<U32>(Opcode::MinSigned32, a, b);
}
return Inst<U64>(Opcode::MinSigned64, a, b);
}
U32U64 IREmitter::MinUnsigned(const U32U64& a, const U32U64& b) {
if (a.GetType() == IR::Type::U32) {
return Inst<U32>(Opcode::MinUnsigned32, a, b);
}
return Inst<U64>(Opcode::MinUnsigned64, a, b);
}
ResultAndOverflow<U32> IREmitter::SignedSaturatedAdd(const U32& a, const U32& b) {
auto result = Inst<U32>(Opcode::SignedSaturatedAdd, a, b);
auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);

4
src/frontend/ir/ir_emitter.h
View file

@ -137,6 +137,10 @@ public:
U64 ByteReverseDual(const U64& a);
U32U64 CountLeadingZeros(const U32U64& a);
U32U64 ExtractRegister(const U32U64& a, const U32U64& b, const U8& lsb);
U32U64 MaxSigned(const U32U64& a, const U32U64& b);
U32U64 MaxUnsigned(const U32U64& a, const U32U64& b);
U32U64 MinSigned(const U32U64& a, const U32U64& b);
U32U64 MinUnsigned(const U32U64& a, const U32U64& b);
ResultAndOverflow<U32> SignedSaturatedAdd(const U32& a, const U32& b);
ResultAndOverflow<U32> SignedSaturatedSub(const U32& a, const U32& b);

8
src/frontend/ir/opcodes.inc
View file

@ -145,6 +145,14 @@ OPCODE(CountLeadingZeros32, T::U32, T::U32
OPCODE(CountLeadingZeros64, T::U64, T::U64 )
OPCODE(ExtractRegister32, T::U32, T::U32, T::U32, T::U8 )
OPCODE(ExtractRegister64, T::U64, T::U64, T::U64, T::U8 )
OPCODE(MaxSigned32, T::U32, T::U32, T::U32 )
OPCODE(MaxSigned64, T::U64, T::U64, T::U64 )
OPCODE(MaxUnsigned32, T::U32, T::U32, T::U32 )
OPCODE(MaxUnsigned64, T::U64, T::U64, T::U64 )
OPCODE(MinSigned32, T::U32, T::U32, T::U32 )
OPCODE(MinSigned64, T::U64, T::U64, T::U64 )
OPCODE(MinUnsigned32, T::U32, T::U32, T::U32 )
OPCODE(MinUnsigned64, T::U64, T::U64, T::U64 )
// Saturated instructions
OPCODE(SignedSaturatedAdd, T::U32, T::U32, T::U32 )