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reg_alloc: Use a strongly-typed enum for representing OpArg type (#15)

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Mat M 2016-09-03 13:30:03 -04:00 committed by Merry
parent 05b189bc26
commit 26db11cd71
1 changed files with 16 additions and 14 deletions
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30
src/backend_x64/reg_alloc.h
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@ -24,17 +24,17 @@ namespace Dynarmic {
namespace BackendX64 { namespace BackendX64 {
struct OpArg { struct OpArg {
OpArg() : type(OPERAND), inner_operand() {} OpArg() : type(Type::Operand), inner_operand() {}
OpArg(const Xbyak::Address& address) : type(ADDRESS), inner_address(address) {} OpArg(const Xbyak::Address& address) : type(Type::Address), inner_address(address) {}
OpArg(const Xbyak::Reg& reg) : type(REG), inner_reg(reg) {} OpArg(const Xbyak::Reg& reg) : type(Type::Reg), inner_reg(reg) {}
Xbyak::Operand& operator*() { Xbyak::Operand& operator*() {
switch (type) { switch (type) {
case ADDRESS: case Type::Address:
return inner_address; return inner_address;
case OPERAND: case Type::Operand:
return inner_operand; return inner_operand;
case REG: case Type::Reg:
return inner_reg; return inner_reg;
} }
ASSERT_MSG(false, "Unreachable"); ASSERT_MSG(false, "Unreachable");
@ -42,13 +42,13 @@ struct OpArg {
void setBit(int bits) { void setBit(int bits) {
switch (type) { switch (type) {
case ADDRESS: case Type::Address:
inner_address.setBit(bits); inner_address.setBit(bits);
return; return;
case OPERAND: case Type::Operand:
inner_operand.setBit(bits); inner_operand.setBit(bits);
return; return;
case REG: case Type::Reg:
switch (bits) { switch (bits) {
case 8: case 8:
inner_reg = inner_reg.cvt8(); inner_reg = inner_reg.cvt8();
@ -71,11 +71,13 @@ struct OpArg {
} }
private: private:
enum { enum class Type {
OPERAND, Operand,
ADDRESS, Address,
REG, Reg,
} type; };
Type type;
union { union {
Xbyak::Operand inner_operand; Xbyak::Operand inner_operand;