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A64: Implement FRECPE, scalar single/double variant

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This commit is contained in:
MerryMage 2018-07-25 18:47:45 +01:00
parent fc2d33ae7b
commit 27c73dd56a
2 changed files with 11 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -377,7 +377,7 @@ INST(FCVTPS_2, "FCVTPS (vector)", "01011
//INST(FCVTZS_int_1, "FCVTZS (vector, integer)", "0101111011111001101110nnnnnddddd")
INST(FCVTZS_int_2, "FCVTZS (vector, integer)", "010111101z100001101110nnnnnddddd")
//INST(FRECPE_1, "FRECPE", "0101111011111001110110nnnnnddddd")
//INST(FRECPE_2, "FRECPE", "010111101z100001110110nnnnnddddd")
INST(FRECPE_2, "FRECPE", "010111101z100001110110nnnnnddddd")
//INST(FRECPX_1, "FRECPX", "0101111011111001111110nnnnnddddd")
//INST(FRECPX_2, "FRECPX", "010111101z100001111110nnnnnddddd")
//INST(FCVTNU_1, "FCVTNU (vector)", "0111111001111001101010nnnnnddddd")

10
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
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@ -148,6 +148,16 @@ bool TranslatorVisitor::FCVTZU_int_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Unsigned);
}
bool TranslatorVisitor::FRECPE_2(bool sz, Vec Vn, Vec Vd) {
const size_t esize = sz ? 64 : 32;
const IR::U32U64 operand = V_scalar(esize, Vn);
const IR::U32U64 result = ir.FPRecipEstimate(operand);
V_scalar(esize, Vd, result);
return true;
}
bool TranslatorVisitor::FRSQRTE_2(bool sz, Vec Vn, Vec Vd) {
const size_t esize = sz ? 64 : 32;