A32: Implement ARM-mode BFI

src/frontend/A32/decoder/arm.inc

@@ -165,6 +165,7 @@ INST(arm_STM_usr,       "STM (usr reg)",       "----100--100--------------------
 
 // Miscellaneous instructions
 INST(arm_BFC,           "BFC",                 "cccc0111110vvvvvddddvvvvv0011111") // v6T2
+INST(arm_BFI,           "BFI",                 "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
 INST(arm_CLZ,           "CLZ",                 "cccc000101101111dddd11110001mmmm") // v5
 INST(arm_NOP,           "NOP",                 "----0011001000001111000000000000") // v6K
 INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6

src/frontend/A32/disassembler/disassembler_arm.cpp

@@ -586,6 +586,9 @@ public:
     std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
         return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1);
     }
+    std::string arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) {
+        return fmt::format("bfi{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, msb - lsb + 1);
+    }
     std::string arm_CLZ(Cond cond, Reg d, Reg m) {
         return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
     }

src/frontend/A32/translate/translate_arm/misc.cpp

@@ -30,6 +30,29 @@ bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
     return true;
 }
 
+// BFI<c> <Rd>, <Rn>, #<lsb>, #<width>
+bool ArmTranslatorVisitor::arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) {
+    if (d == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+    if (msb < lsb) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const u32 inclusion_mask = Common::Ones<u32>(msb - lsb + 1) << lsb;
+    const u32 exclusion_mask = ~inclusion_mask;
+    const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask));
+    const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(lsb)), ir.Imm32(inclusion_mask));
+    const IR::U32 result = ir.Or(operand1, operand2);
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 // CLZ<c> <Rd>, <Rm>
 bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
     if (d == Reg::PC || m == Reg::PC) {

src/frontend/A32/translate/translate_arm/translate_arm.h

@@ -208,6 +208,7 @@ struct ArmTranslatorVisitor final {
 
     // Miscellaneous instructions
     bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb);
+    bool arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n);
     bool arm_CLZ(Cond cond, Reg d, Reg m);
     bool arm_NOP() { return true; }
     bool arm_RBIT(Cond cond, Reg d, Reg m);

tests/A32/fuzz_arm.cpp

@@ -1080,7 +1080,7 @@ TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][.vfp][A32]") {
 }
 
 TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
-    const auto is_bfc_valid = [](u32 instr) {
+    const auto is_bfc_bfi_valid = [](u32 instr) {
         if (Bits<12, 15>(instr) == 0b1111) {
             // Destination register may not be the PC.
             return false;
@@ -1095,8 +1095,9 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
     };
 
     const std::array instructions = {
-        InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_valid), // BFC
+        InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC
-        InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ
+        InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI
+        InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid),     // CLZ
     };
 
     FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {