A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
This commit is contained in:
MerryMage
parent
7b33772ac6
commit
2a0850c068
2 changed files with 117 additions and 117 deletions
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@ -329,40 +329,22 @@ INST(AESIMC, "AESIMC", "01001
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// Data Processing - FP and SIMD - Scalar three
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// Data Processing - FP and SIMD - Scalar three
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//INST(FMULX_vec_1, "FMULX", "01011110010mmmmm000111nnnnnddddd")
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//INST(FMULX_vec_1, "FMULX", "01011110010mmmmm000111nnnnnddddd")
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//INST(FMULX_vec_2, "FMULX", "010111100z1mmmmm110111nnnnnddddd")
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//INST(FMULX_vec_2, "FMULX", "010111100z1mmmmm110111nnnnnddddd")
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//INST(FMULX_vec_3, "FMULX", "0Q001110010mmmmm000111nnnnnddddd")
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//INST(FMULX_vec_4, "FMULX", "0Q0011100z1mmmmm110111nnnnnddddd")
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//INST(FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd")
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//INST(FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd")
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//INST(FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd")
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//INST(FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd")
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//INST(FCMEQ_reg_3, "FCMEQ (register)", "0Q001110010mmmmm001001nnnnnddddd")
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//INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd")
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//INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd")
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//INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd")
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//INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd")
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//INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd")
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//INST(FRECPS_3, "FRECPS", "0Q001110010mmmmm001111nnnnnddddd")
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//INST(FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd")
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//INST(FRSQRTS_1, "FRSQRTS", "01011110110mmmmm001111nnnnnddddd")
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//INST(FRSQRTS_1, "FRSQRTS", "01011110110mmmmm001111nnnnnddddd")
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//INST(FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd")
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//INST(FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd")
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//INST(FRSQRTS_3, "FRSQRTS", "0Q001110110mmmmm001111nnnnnddddd")
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//INST(FRSQRTS_4, "FRSQRTS", "0Q0011101z1mmmmm111111nnnnnddddd")
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//INST(FCMGE_reg_1, "FCMGE (register)", "01111110010mmmmm001001nnnnnddddd")
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//INST(FCMGE_reg_1, "FCMGE (register)", "01111110010mmmmm001001nnnnnddddd")
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//INST(FCMGE_reg_2, "FCMGE (register)", "011111100z1mmmmm111001nnnnnddddd")
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//INST(FCMGE_reg_2, "FCMGE (register)", "011111100z1mmmmm111001nnnnnddddd")
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//INST(FCMGE_reg_3, "FCMGE (register)", "0Q101110010mmmmm001001nnnnnddddd")
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//INST(FCMGE_reg_4, "FCMGE (register)", "0Q1011100z1mmmmm111001nnnnnddddd")
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//INST(FACGE_1, "FACGE", "01111110010mmmmm001011nnnnnddddd")
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//INST(FACGE_1, "FACGE", "01111110010mmmmm001011nnnnnddddd")
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//INST(FACGE_2, "FACGE", "011111100z1mmmmm111011nnnnnddddd")
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//INST(FACGE_2, "FACGE", "011111100z1mmmmm111011nnnnnddddd")
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//INST(FACGE_3, "FACGE", "0Q101110010mmmmm001011nnnnnddddd")
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//INST(FACGE_4, "FACGE", "0Q1011100z1mmmmm111011nnnnnddddd")
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//INST(FABD_1, "FABD", "01111110110mmmmm000101nnnnnddddd")
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//INST(FABD_1, "FABD", "01111110110mmmmm000101nnnnnddddd")
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//INST(FABD_2, "FABD", "011111101z1mmmmm110101nnnnnddddd")
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//INST(FABD_2, "FABD", "011111101z1mmmmm110101nnnnnddddd")
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//INST(FABD_3, "FABD", "0Q101110110mmmmm000101nnnnnddddd")
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//INST(FABD_4, "FABD", "0Q1011101z1mmmmm110101nnnnnddddd")
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//INST(FCMGT_reg_1, "FCMGT (register)", "01111110110mmmmm001001nnnnnddddd")
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//INST(FCMGT_reg_1, "FCMGT (register)", "01111110110mmmmm001001nnnnnddddd")
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//INST(FCMGT_reg_2, "FCMGT (register)", "011111101z1mmmmm111001nnnnnddddd")
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//INST(FCMGT_reg_2, "FCMGT (register)", "011111101z1mmmmm111001nnnnnddddd")
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//INST(FCMGT_reg_3, "FCMGT (register)", "0Q101110110mmmmm001001nnnnnddddd")
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//INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd")
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//INST(FACGT_1, "FACGT", "01111110110mmmmm001011nnnnnddddd")
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//INST(FACGT_1, "FACGT", "01111110110mmmmm001011nnnnnddddd")
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//INST(FACGT_2, "FACGT", "011111101z1mmmmm111011nnnnnddddd")
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//INST(FACGT_2, "FACGT", "011111101z1mmmmm111011nnnnnddddd")
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//INST(FACGT_3, "FACGT", "0Q101110110mmmmm001011nnnnnddddd")
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//INST(FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd")
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// Data Processing - FP and SIMD - Two register misc
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// Data Processing - FP and SIMD - Two register misc
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//INST(FCVTNS_1, "FCVTNS (vector)", "0101111001111001101010nnnnnddddd")
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//INST(FCVTNS_1, "FCVTNS (vector)", "0101111001111001101010nnnnnddddd")
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@ -505,49 +487,27 @@ INST(AESIMC, "AESIMC", "01001
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// Data Processing - FP and SIMD - SIMD Scalar three same
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// Data Processing - FP and SIMD - SIMD Scalar three same
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//INST(SQADD_1, "SQADD", "01011110zz1mmmmm000011nnnnnddddd")
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//INST(SQADD_1, "SQADD", "01011110zz1mmmmm000011nnnnnddddd")
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//INST(SQADD_2, "SQADD", "0Q001110zz1mmmmm000011nnnnnddddd")
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//INST(SQSUB_1, "SQSUB", "01011110zz1mmmmm001011nnnnnddddd")
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//INST(SQSUB_1, "SQSUB", "01011110zz1mmmmm001011nnnnnddddd")
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//INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd")
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//INST(CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd")
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//INST(CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd")
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//INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd")
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//INST(CMGE_reg_1, "CMGE (register)", "01011110zz1mmmmm001111nnnnnddddd")
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//INST(CMGE_reg_1, "CMGE (register)", "01011110zz1mmmmm001111nnnnnddddd")
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//INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd")
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//INST(SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd")
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//INST(SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd")
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//INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd")
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//INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")
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//INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")
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//INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd")
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//INST(SRSHL_1, "SRSHL", "01011110zz1mmmmm010101nnnnnddddd")
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//INST(SRSHL_1, "SRSHL", "01011110zz1mmmmm010101nnnnnddddd")
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//INST(SRSHL_2, "SRSHL", "0Q001110zz1mmmmm010101nnnnnddddd")
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//INST(SQRSHL_1, "SQRSHL", "01011110zz1mmmmm010111nnnnnddddd")
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//INST(SQRSHL_1, "SQRSHL", "01011110zz1mmmmm010111nnnnnddddd")
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//INST(SQRSHL_2, "SQRSHL", "0Q001110zz1mmmmm010111nnnnnddddd")
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//INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd")
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//INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd")
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INST(ADD_vector, "ADD (vector)", "0Q001110zz1mmmmm100001nnnnnddddd")
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//INST(CMTST_1, "CMTST", "01011110zz1mmmmm100011nnnnnddddd")
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//INST(CMTST_1, "CMTST", "01011110zz1mmmmm100011nnnnnddddd")
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//INST(CMTST_2, "CMTST", "0Q001110zz1mmmmm100011nnnnnddddd")
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//INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd")
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//INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd")
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//INST(SQDMULH_vec_2, "SQDMULH (vector)", "0Q001110zz1mmmmm101101nnnnnddddd")
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//INST(UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd")
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//INST(UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd")
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//INST(UQADD_2, "UQADD", "0Q101110zz1mmmmm000011nnnnnddddd")
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//INST(UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd")
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//INST(UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd")
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//INST(UQSUB_2, "UQSUB", "0Q101110zz1mmmmm001011nnnnnddddd")
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//INST(CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd")
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//INST(CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd")
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//INST(CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd")
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//INST(CMHS_1, "CMHS (register)", "01111110zz1mmmmm001111nnnnnddddd")
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//INST(CMHS_1, "CMHS (register)", "01111110zz1mmmmm001111nnnnnddddd")
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//INST(CMHS_2, "CMHS (register)", "0Q101110zz1mmmmm001111nnnnnddddd")
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//INST(USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd")
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//INST(USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd")
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//INST(USHL_2, "USHL", "0Q101110zz1mmmmm010001nnnnnddddd")
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//INST(UQSHL_reg_1, "UQSHL (register)", "01111110zz1mmmmm010011nnnnnddddd")
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//INST(UQSHL_reg_1, "UQSHL (register)", "01111110zz1mmmmm010011nnnnnddddd")
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//INST(UQSHL_reg_2, "UQSHL (register)", "0Q101110zz1mmmmm010011nnnnnddddd")
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//INST(URSHL_1, "URSHL", "01111110zz1mmmmm010101nnnnnddddd")
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//INST(URSHL_1, "URSHL", "01111110zz1mmmmm010101nnnnnddddd")
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//INST(URSHL_2, "URSHL", "0Q101110zz1mmmmm010101nnnnnddddd")
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//INST(UQRSHL_1, "UQRSHL", "01111110zz1mmmmm010111nnnnnddddd")
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//INST(UQRSHL_1, "UQRSHL", "01111110zz1mmmmm010111nnnnnddddd")
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//INST(UQRSHL_2, "UQRSHL", "0Q101110zz1mmmmm010111nnnnnddddd")
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//INST(SUB_1, "SUB (vector)", "01111110zz1mmmmm100001nnnnnddddd")
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//INST(SUB_1, "SUB (vector)", "01111110zz1mmmmm100001nnnnnddddd")
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//INST(SUB_2, "SUB (vector)", "0Q101110zz1mmmmm100001nnnnnddddd")
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//INST(CMEQ_reg_1, "CMEQ (register)", "01111110zz1mmmmm100011nnnnnddddd")
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//INST(CMEQ_reg_1, "CMEQ (register)", "01111110zz1mmmmm100011nnnnnddddd")
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INST(CMEQ_reg_2, "CMEQ (register)", "0Q101110zz1mmmmm100011nnnnnddddd")
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//INST(SQRDMULH_vec_1, "SQRDMULH (vector)", "01111110zz1mmmmm101101nnnnnddddd")
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//INST(SQRDMULH_vec_1, "SQRDMULH (vector)", "01111110zz1mmmmm101101nnnnnddddd")
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//INST(SQRDMULH_vec_2, "SQRDMULH (vector)", "0Q101110zz1mmmmm101101nnnnnddddd")
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// Data Processing - FP and SIMD - SIMD Scalar shift by immediate
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// Data Processing - FP and SIMD - SIMD Scalar shift by immediate
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//INST(SSHR_1, "SSHR", "010111110IIIIiii000001nnnnnddddd")
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//INST(SSHR_1, "SSHR", "010111110IIIIiii000001nnnnnddddd")
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@ -601,35 +561,20 @@ INST(CMEQ_reg_2, "CMEQ (register)", "0Q101
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// Data Processing - FP and SIMD - SIMD Scalar x indexed element
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// Data Processing - FP and SIMD - SIMD Scalar x indexed element
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//INST(SQDMLAL_elt_1, "SQDMLAL, SQDMLAL2 (by element)", "01011111zzLMmmmm0011H0nnnnnddddd")
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//INST(SQDMLAL_elt_1, "SQDMLAL, SQDMLAL2 (by element)", "01011111zzLMmmmm0011H0nnnnnddddd")
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//INST(SQDMLAL_elt_2, "SQDMLAL, SQDMLAL2 (by element)", "0Q001111zzLMmmmm0011H0nnnnnddddd")
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//INST(SQDMLSL_elt_1, "SQDMLSL, SQDMLSL2 (by element)", "01011111zzLMmmmm0111H0nnnnnddddd")
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//INST(SQDMLSL_elt_1, "SQDMLSL, SQDMLSL2 (by element)", "01011111zzLMmmmm0111H0nnnnnddddd")
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//INST(SQDMLSL_elt_2, "SQDMLSL, SQDMLSL2 (by element)", "0Q001111zzLMmmmm0111H0nnnnnddddd")
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//INST(SQDMULL_elt_1, "SQDMULL, SQDMULL2 (by element)", "01011111zzLMmmmm1011H0nnnnnddddd")
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//INST(SQDMULL_elt_1, "SQDMULL, SQDMULL2 (by element)", "01011111zzLMmmmm1011H0nnnnnddddd")
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//INST(SQDMULL_elt_2, "SQDMULL, SQDMULL2 (by element)", "0Q001111zzLMmmmm1011H0nnnnnddddd")
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//INST(SQDMULH_elt_1, "SQDMULH (by element)", "01011111zzLMmmmm1100H0nnnnnddddd")
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//INST(SQDMULH_elt_1, "SQDMULH (by element)", "01011111zzLMmmmm1100H0nnnnnddddd")
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//INST(SQDMULH_elt_2, "SQDMULH (by element)", "0Q001111zzLMmmmm1100H0nnnnnddddd")
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//INST(SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd")
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//INST(SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd")
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//INST(SQRDMULH_elt_2, "SQRDMULH (by element)", "0Q001111zzLMmmmm1101H0nnnnnddddd")
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//INST(FMLA_elt_1, "FMLA (by element)", "0101111100LMmmmm0001H0nnnnnddddd")
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//INST(FMLA_elt_1, "FMLA (by element)", "0101111100LMmmmm0001H0nnnnnddddd")
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//INST(FMLA_elt_2, "FMLA (by element)", "010111111zLMmmmm0001H0nnnnnddddd")
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//INST(FMLA_elt_2, "FMLA (by element)", "010111111zLMmmmm0001H0nnnnnddddd")
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//INST(FMLA_elt_3, "FMLA (by element)", "0Q00111100LMmmmm0001H0nnnnnddddd")
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//INST(FMLA_elt_4, "FMLA (by element)", "0Q0011111zLMmmmm0001H0nnnnnddddd")
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//INST(FMLS_elt_1, "FMLS (by element)", "0101111100LMmmmm0101H0nnnnnddddd")
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//INST(FMLS_elt_1, "FMLS (by element)", "0101111100LMmmmm0101H0nnnnnddddd")
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//INST(FMLS_elt_2, "FMLS (by element)", "010111111zLMmmmm0101H0nnnnnddddd")
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//INST(FMLS_elt_2, "FMLS (by element)", "010111111zLMmmmm0101H0nnnnnddddd")
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//INST(FMLS_elt_3, "FMLS (by element)", "0Q00111100LMmmmm0101H0nnnnnddddd")
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//INST(FMLS_elt_4, "FMLS (by element)", "0Q0011111zLMmmmm0101H0nnnnnddddd")
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//INST(FMUL_elt_1, "FMUL (by element)", "0101111100LMmmmm1001H0nnnnnddddd")
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//INST(FMUL_elt_1, "FMUL (by element)", "0101111100LMmmmm1001H0nnnnnddddd")
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//INST(FMUL_elt_2, "FMUL (by element)", "010111111zLMmmmm1001H0nnnnnddddd")
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//INST(FMUL_elt_2, "FMUL (by element)", "010111111zLMmmmm1001H0nnnnnddddd")
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//INST(FMUL_elt_3, "FMUL (by element)", "0Q00111100LMmmmm1001H0nnnnnddddd")
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//INST(FMUL_elt_4, "FMUL (by element)", "0Q0011111zLMmmmm1001H0nnnnnddddd")
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//INST(SQRDMLAH_elt_1, "SQRDMLAH (by element)", "01111111zzLMmmmm1101H0nnnnnddddd")
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//INST(SQRDMLAH_elt_1, "SQRDMLAH (by element)", "01111111zzLMmmmm1101H0nnnnnddddd")
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//INST(SQRDMLAH_elt_2, "SQRDMLAH (by element)", "0Q101111zzLMmmmm1101H0nnnnnddddd")
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//INST(SQRDMLSH_elt_1, "SQRDMLSH (by element)", "01111111zzLMmmmm1111H0nnnnnddddd")
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//INST(SQRDMLSH_elt_1, "SQRDMLSH (by element)", "01111111zzLMmmmm1111H0nnnnnddddd")
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//INST(SQRDMLSH_elt_2, "SQRDMLSH (by element)", "0Q101111zzLMmmmm1111H0nnnnnddddd")
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//INST(FMULX_elt_1, "FMULX (by element)", "0111111100LMmmmm1001H0nnnnnddddd")
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//INST(FMULX_elt_1, "FMULX (by element)", "0111111100LMmmmm1001H0nnnnnddddd")
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//INST(FMULX_elt_2, "FMULX (by element)", "011111111zLMmmmm1001H0nnnnnddddd")
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//INST(FMULX_elt_2, "FMULX (by element)", "011111111zLMmmmm1001H0nnnnnddddd")
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//INST(FMULX_elt_3, "FMULX (by element)", "0Q10111100LMmmmm1001H0nnnnnddddd")
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//INST(FMULX_elt_4, "FMULX (by element)", "0Q1011111zLMmmmm1001H0nnnnnddddd")
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// Data Processing - FP and SIMD - SIMD Table Lookup
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// Data Processing - FP and SIMD - SIMD Table Lookup
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//INST(TBL, "TBL", "0Q001110000mmmmm0LL000nnnnnddddd")
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//INST(TBL, "TBL", "0Q001110000mmmmm0LL000nnnnnddddd")
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@ -654,36 +599,30 @@ INST(INS_gen, "INS (general)", "01001
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INST(INS_elt, "INS (element)", "01101110000iiiii0iiii1nnnnnddddd")
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INST(INS_elt, "INS (element)", "01101110000iiiii0iiii1nnnnnddddd")
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||||||
|
|
||||||
// Data Processing - FP and SIMD - SIMD Three same
|
// Data Processing - FP and SIMD - SIMD Three same
|
||||||
|
//INST(FMULX_vec_3, "FMULX", "0Q001110010mmmmm000111nnnnnddddd")
|
||||||
|
//INST(FCMEQ_reg_3, "FCMEQ (register)", "0Q001110010mmmmm001001nnnnnddddd")
|
||||||
|
//INST(FRECPS_3, "FRECPS", "0Q001110010mmmmm001111nnnnnddddd")
|
||||||
|
//INST(FRSQRTS_3, "FRSQRTS", "0Q001110110mmmmm001111nnnnnddddd")
|
||||||
|
//INST(FCMGE_reg_3, "FCMGE (register)", "0Q101110010mmmmm001001nnnnnddddd")
|
||||||
|
//INST(FACGE_3, "FACGE", "0Q101110010mmmmm001011nnnnnddddd")
|
||||||
|
//INST(FABD_3, "FABD", "0Q101110110mmmmm000101nnnnnddddd")
|
||||||
|
//INST(FCMGT_reg_3, "FCMGT (register)", "0Q101110110mmmmm001001nnnnnddddd")
|
||||||
|
//INST(FACGT_3, "FACGT", "0Q101110110mmmmm001011nnnnnddddd")
|
||||||
//INST(FMAXNM_1, "FMAXNM (vector)", "0Q001110010mmmmm000001nnnnnddddd")
|
//INST(FMAXNM_1, "FMAXNM (vector)", "0Q001110010mmmmm000001nnnnnddddd")
|
||||||
//INST(FMAXNM_2, "FMAXNM (vector)", "0Q0011100z1mmmmm110001nnnnnddddd")
|
|
||||||
//INST(FMLA_vec_1, "FMLA (vector)", "0Q001110010mmmmm000011nnnnnddddd")
|
//INST(FMLA_vec_1, "FMLA (vector)", "0Q001110010mmmmm000011nnnnnddddd")
|
||||||
//INST(FMLA_vec_2, "FMLA (vector)", "0Q0011100z1mmmmm110011nnnnnddddd")
|
|
||||||
//INST(FADD_1, "FADD (vector)", "0Q001110010mmmmm000101nnnnnddddd")
|
//INST(FADD_1, "FADD (vector)", "0Q001110010mmmmm000101nnnnnddddd")
|
||||||
//INST(FADD_2, "FADD (vector)", "0Q0011100z1mmmmm110101nnnnnddddd")
|
|
||||||
//INST(FMAX_1, "FMAX (vector)", "0Q001110010mmmmm001101nnnnnddddd")
|
//INST(FMAX_1, "FMAX (vector)", "0Q001110010mmmmm001101nnnnnddddd")
|
||||||
//INST(FMAX_2, "FMAX (vector)", "0Q0011100z1mmmmm111101nnnnnddddd")
|
|
||||||
//INST(FMINNM_1, "FMINNM (vector)", "0Q001110110mmmmm000001nnnnnddddd")
|
//INST(FMINNM_1, "FMINNM (vector)", "0Q001110110mmmmm000001nnnnnddddd")
|
||||||
//INST(FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd")
|
|
||||||
//INST(FMLS_vec_1, "FMLS (vector)", "0Q001110110mmmmm000011nnnnnddddd")
|
//INST(FMLS_vec_1, "FMLS (vector)", "0Q001110110mmmmm000011nnnnnddddd")
|
||||||
//INST(FMLS_vec_2, "FMLS (vector)", "0Q0011101z1mmmmm110011nnnnnddddd")
|
|
||||||
//INST(FSUB_1, "FSUB (vector)", "0Q001110110mmmmm000101nnnnnddddd")
|
//INST(FSUB_1, "FSUB (vector)", "0Q001110110mmmmm000101nnnnnddddd")
|
||||||
//INST(FSUB_2, "FSUB (vector)", "0Q0011101z1mmmmm110101nnnnnddddd")
|
|
||||||
//INST(FMIN_1, "FMIN (vector)", "0Q001110110mmmmm001101nnnnnddddd")
|
//INST(FMIN_1, "FMIN (vector)", "0Q001110110mmmmm001101nnnnnddddd")
|
||||||
//INST(FMIN_2, "FMIN (vector)", "0Q0011101z1mmmmm111101nnnnnddddd")
|
|
||||||
//INST(FMAXNMP_vec_1, "FMAXNMP (vector)", "0Q101110010mmmmm000001nnnnnddddd")
|
//INST(FMAXNMP_vec_1, "FMAXNMP (vector)", "0Q101110010mmmmm000001nnnnnddddd")
|
||||||
//INST(FMAXNMP_vec_2, "FMAXNMP (vector)", "0Q1011100z1mmmmm110001nnnnnddddd")
|
|
||||||
//INST(FADDP_vec_1, "FADDP (vector)", "0Q101110010mmmmm000101nnnnnddddd")
|
//INST(FADDP_vec_1, "FADDP (vector)", "0Q101110010mmmmm000101nnnnnddddd")
|
||||||
//INST(FADDP_vec_2, "FADDP (vector)", "0Q1011100z1mmmmm110101nnnnnddddd")
|
|
||||||
//INST(FMUL_vec_1, "FMUL (vector)", "0Q101110010mmmmm000111nnnnnddddd")
|
//INST(FMUL_vec_1, "FMUL (vector)", "0Q101110010mmmmm000111nnnnnddddd")
|
||||||
//INST(FMUL_vec_2, "FMUL (vector)", "0Q1011100z1mmmmm110111nnnnnddddd")
|
|
||||||
//INST(FMAXP_vec_1, "FMAXP (vector)", "0Q101110010mmmmm001101nnnnnddddd")
|
//INST(FMAXP_vec_1, "FMAXP (vector)", "0Q101110010mmmmm001101nnnnnddddd")
|
||||||
//INST(FMAXP_vec_2, "FMAXP (vector)", "0Q1011100z1mmmmm111101nnnnnddddd")
|
|
||||||
//INST(FDIV_1, "FDIV (vector)", "0Q101110010mmmmm001111nnnnnddddd")
|
//INST(FDIV_1, "FDIV (vector)", "0Q101110010mmmmm001111nnnnnddddd")
|
||||||
//INST(FDIV_2, "FDIV (vector)", "0Q1011100z1mmmmm111111nnnnnddddd")
|
|
||||||
//INST(FMINNMP_vec_1, "FMINNMP (vector)", "0Q101110110mmmmm000001nnnnnddddd")
|
//INST(FMINNMP_vec_1, "FMINNMP (vector)", "0Q101110110mmmmm000001nnnnnddddd")
|
||||||
//INST(FMINNMP_vec_2, "FMINNMP (vector)", "0Q1011101z1mmmmm110001nnnnnddddd")
|
|
||||||
//INST(FMINP_vec_1, "FMINP (vector)", "0Q101110110mmmmm001101nnnnnddddd")
|
//INST(FMINP_vec_1, "FMINP (vector)", "0Q101110110mmmmm001101nnnnnddddd")
|
||||||
//INST(FMINP_vec_2, "FMINP (vector)", "0Q1011101z1mmmmm111101nnnnnddddd")
|
|
||||||
|
|
||||||
// Data Processing - FP and SIMD - SIMD Two-register misc
|
// Data Processing - FP and SIMD - SIMD Two-register misc
|
||||||
//INST(FRINTN_1, "FRINTN (vector)", "0Q00111001111001100010nnnnnddddd")
|
//INST(FRINTN_1, "FRINTN (vector)", "0Q00111001111001100010nnnnnddddd")
|
||||||
|
|
@ -777,38 +716,84 @@ INST(INS_elt, "INS (element)", "01101
|
||||||
|
|
||||||
// Data Processing - FP and SIMD - SIMD three same
|
// Data Processing - FP and SIMD - SIMD three same
|
||||||
//INST(SHADD, "SHADD", "0Q001110zz1mmmmm000001nnnnnddddd")
|
//INST(SHADD, "SHADD", "0Q001110zz1mmmmm000001nnnnnddddd")
|
||||||
|
//INST(SQADD_2, "SQADD", "0Q001110zz1mmmmm000011nnnnnddddd")
|
||||||
//INST(SRHADD, "SRHADD", "0Q001110zz1mmmmm000101nnnnnddddd")
|
//INST(SRHADD, "SRHADD", "0Q001110zz1mmmmm000101nnnnnddddd")
|
||||||
//INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd")
|
//INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd")
|
||||||
|
//INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd")
|
||||||
|
//INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd")
|
||||||
|
//INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd")
|
||||||
|
//INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd")
|
||||||
|
//INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd")
|
||||||
|
//INST(SRSHL_2, "SRSHL", "0Q001110zz1mmmmm010101nnnnnddddd")
|
||||||
|
//INST(SQRSHL_2, "SQRSHL", "0Q001110zz1mmmmm010111nnnnnddddd")
|
||||||
//INST(SMAX, "SMAX", "0Q001110zz1mmmmm011001nnnnnddddd")
|
//INST(SMAX, "SMAX", "0Q001110zz1mmmmm011001nnnnnddddd")
|
||||||
//INST(SMIN, "SMIN", "0Q001110zz1mmmmm011011nnnnnddddd")
|
//INST(SMIN, "SMIN", "0Q001110zz1mmmmm011011nnnnnddddd")
|
||||||
//INST(SABD, "SABD", "0Q001110zz1mmmmm011101nnnnnddddd")
|
//INST(SABD, "SABD", "0Q001110zz1mmmmm011101nnnnnddddd")
|
||||||
//INST(SABA, "SABA", "0Q001110zz1mmmmm011111nnnnnddddd")
|
//INST(SABA, "SABA", "0Q001110zz1mmmmm011111nnnnnddddd")
|
||||||
|
INST(ADD_vector, "ADD (vector)", "0Q001110zz1mmmmm100001nnnnnddddd")
|
||||||
|
//INST(CMTST_2, "CMTST", "0Q001110zz1mmmmm100011nnnnnddddd")
|
||||||
//INST(MLA_vec, "MLA (vector)", "0Q001110zz1mmmmm100101nnnnnddddd")
|
//INST(MLA_vec, "MLA (vector)", "0Q001110zz1mmmmm100101nnnnnddddd")
|
||||||
//INST(MUL_vec, "MUL (vector)", "0Q001110zz1mmmmm100111nnnnnddddd")
|
//INST(MUL_vec, "MUL (vector)", "0Q001110zz1mmmmm100111nnnnnddddd")
|
||||||
//INST(SMAXP, "SMAXP", "0Q001110zz1mmmmm101001nnnnnddddd")
|
//INST(SMAXP, "SMAXP", "0Q001110zz1mmmmm101001nnnnnddddd")
|
||||||
//INST(SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd")
|
//INST(SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd")
|
||||||
|
//INST(SQDMULH_vec_2, "SQDMULH (vector)", "0Q001110zz1mmmmm101101nnnnnddddd")
|
||||||
INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd")
|
INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd")
|
||||||
|
//INST(FMAXNM_2, "FMAXNM (vector)", "0Q0011100z1mmmmm110001nnnnnddddd")
|
||||||
|
//INST(FMLA_vec_2, "FMLA (vector)", "0Q0011100z1mmmmm110011nnnnnddddd")
|
||||||
|
//INST(FADD_2, "FADD (vector)", "0Q0011100z1mmmmm110101nnnnnddddd")
|
||||||
|
//INST(FMAX_2, "FMAX (vector)", "0Q0011100z1mmmmm111101nnnnnddddd")
|
||||||
|
//INST(FMULX_vec_4, "FMULX", "0Q0011100z1mmmmm110111nnnnnddddd")
|
||||||
|
//INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd")
|
||||||
//INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd")
|
//INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd")
|
||||||
//INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd")
|
//INST(FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd")
|
||||||
INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")
|
INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")
|
||||||
INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
|
INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
|
||||||
|
//INST(FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd")
|
||||||
|
//INST(FMLS_vec_2, "FMLS (vector)", "0Q0011101z1mmmmm110011nnnnnddddd")
|
||||||
|
//INST(FSUB_2, "FSUB (vector)", "0Q0011101z1mmmmm110101nnnnnddddd")
|
||||||
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")
|
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")
|
||||||
//INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd")
|
//INST(FMIN_2, "FMIN (vector)", "0Q0011101z1mmmmm111101nnnnnddddd")
|
||||||
|
//INST(FRSQRTS_4, "FRSQRTS", "0Q0011101z1mmmmm111111nnnnnddddd")
|
||||||
INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd")
|
INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd")
|
||||||
INST(ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd")
|
INST(ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd")
|
||||||
//INST(UHADD, "UHADD", "0Q101110zz1mmmmm000001nnnnnddddd")
|
//INST(UHADD, "UHADD", "0Q101110zz1mmmmm000001nnnnnddddd")
|
||||||
|
//INST(UQADD_2, "UQADD", "0Q101110zz1mmmmm000011nnnnnddddd")
|
||||||
//INST(URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd")
|
//INST(URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd")
|
||||||
//INST(UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd")
|
//INST(UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd")
|
||||||
|
//INST(UQSUB_2, "UQSUB", "0Q101110zz1mmmmm001011nnnnnddddd")
|
||||||
|
//INST(CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd")
|
||||||
|
//INST(CMHS_2, "CMHS (register)", "0Q101110zz1mmmmm001111nnnnnddddd")
|
||||||
|
//INST(USHL_2, "USHL", "0Q101110zz1mmmmm010001nnnnnddddd")
|
||||||
|
//INST(UQSHL_reg_2, "UQSHL (register)", "0Q101110zz1mmmmm010011nnnnnddddd")
|
||||||
|
//INST(URSHL_2, "URSHL", "0Q101110zz1mmmmm010101nnnnnddddd")
|
||||||
|
//INST(UQRSHL_2, "UQRSHL", "0Q101110zz1mmmmm010111nnnnnddddd")
|
||||||
//INST(UMAX, "UMAX", "0Q101110zz1mmmmm011001nnnnnddddd")
|
//INST(UMAX, "UMAX", "0Q101110zz1mmmmm011001nnnnnddddd")
|
||||||
//INST(UMIN, "UMIN", "0Q101110zz1mmmmm011011nnnnnddddd")
|
//INST(UMIN, "UMIN", "0Q101110zz1mmmmm011011nnnnnddddd")
|
||||||
//INST(UABD, "UABD", "0Q101110zz1mmmmm011101nnnnnddddd")
|
//INST(UABD, "UABD", "0Q101110zz1mmmmm011101nnnnnddddd")
|
||||||
//INST(UABA, "UABA", "0Q101110zz1mmmmm011111nnnnnddddd")
|
//INST(UABA, "UABA", "0Q101110zz1mmmmm011111nnnnnddddd")
|
||||||
|
//INST(SUB_2, "SUB (vector)", "0Q101110zz1mmmmm100001nnnnnddddd")
|
||||||
|
INST(CMEQ_reg_2, "CMEQ (register)", "0Q101110zz1mmmmm100011nnnnnddddd")
|
||||||
//INST(MLS_vec, "MLS (vector)", "0Q101110zz1mmmmm100101nnnnnddddd")
|
//INST(MLS_vec, "MLS (vector)", "0Q101110zz1mmmmm100101nnnnnddddd")
|
||||||
//INST(PMUL, "PMUL", "0Q101110zz1mmmmm100111nnnnnddddd")
|
//INST(PMUL, "PMUL", "0Q101110zz1mmmmm100111nnnnnddddd")
|
||||||
//INST(UMAXP, "UMAXP", "0Q101110zz1mmmmm101001nnnnnddddd")
|
//INST(UMAXP, "UMAXP", "0Q101110zz1mmmmm101001nnnnnddddd")
|
||||||
//INST(UMINP, "UMINP", "0Q101110zz1mmmmm101011nnnnnddddd")
|
//INST(UMINP, "UMINP", "0Q101110zz1mmmmm101011nnnnnddddd")
|
||||||
|
//INST(SQRDMULH_vec_2, "SQRDMULH (vector)", "0Q101110zz1mmmmm101101nnnnnddddd")
|
||||||
|
//INST(FMAXNMP_vec_2, "FMAXNMP (vector)", "0Q1011100z1mmmmm110001nnnnnddddd")
|
||||||
|
//INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd")
|
||||||
|
//INST(FADDP_vec_2, "FADDP (vector)", "0Q1011100z1mmmmm110101nnnnnddddd")
|
||||||
|
//INST(FMUL_vec_2, "FMUL (vector)", "0Q1011100z1mmmmm110111nnnnnddddd")
|
||||||
|
//INST(FCMGE_reg_4, "FCMGE (register)", "0Q1011100z1mmmmm111001nnnnnddddd")
|
||||||
|
//INST(FACGE_4, "FACGE", "0Q1011100z1mmmmm111011nnnnnddddd")
|
||||||
|
//INST(FMAXP_vec_2, "FMAXP (vector)", "0Q1011100z1mmmmm111101nnnnnddddd")
|
||||||
|
//INST(FDIV_2, "FDIV (vector)", "0Q1011100z1mmmmm111111nnnnnddddd")
|
||||||
INST(EOR_asimd, "EOR (vector)", "0Q101110001mmmmm000111nnnnnddddd")
|
INST(EOR_asimd, "EOR (vector)", "0Q101110001mmmmm000111nnnnnddddd")
|
||||||
//INST(BSL, "BSL", "0Q101110011mmmmm000111nnnnnddddd")
|
//INST(BSL, "BSL", "0Q101110011mmmmm000111nnnnnddddd")
|
||||||
|
//INST(FMINNMP_vec_2, "FMINNMP (vector)", "0Q1011101z1mmmmm110001nnnnnddddd")
|
||||||
|
//INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd")
|
||||||
|
//INST(FABD_4, "FABD", "0Q1011101z1mmmmm110101nnnnnddddd")
|
||||||
|
//INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd")
|
||||||
|
//INST(FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd")
|
||||||
|
//INST(FMINP_vec_2, "FMINP (vector)", "0Q1011101z1mmmmm111101nnnnnddddd")
|
||||||
//INST(BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd")
|
//INST(BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd")
|
||||||
//INST(BIF, "BIF", "0Q101110111mmmmm000111nnnnnddddd")
|
//INST(BIF, "BIF", "0Q101110111mmmmm000111nnnnnddddd")
|
||||||
|
|
||||||
|
|
@ -828,10 +813,21 @@ INST(EOR_asimd, "EOR (vector)", "0Q101
|
||||||
|
|
||||||
// Data Processing - FP and SIMD - SIMD x indexed element
|
// Data Processing - FP and SIMD - SIMD x indexed element
|
||||||
//INST(SMLAL_elt, "SMLAL, SMLAL2 (by element)", "0Q001111zzLMmmmm0010H0nnnnnddddd")
|
//INST(SMLAL_elt, "SMLAL, SMLAL2 (by element)", "0Q001111zzLMmmmm0010H0nnnnnddddd")
|
||||||
|
//INST(SQDMLAL_elt_2, "SQDMLAL, SQDMLAL2 (by element)", "0Q001111zzLMmmmm0011H0nnnnnddddd")
|
||||||
//INST(SMLSL_elt, "SMLSL, SMLSL2 (by element)", "0Q001111zzLMmmmm0110H0nnnnnddddd")
|
//INST(SMLSL_elt, "SMLSL, SMLSL2 (by element)", "0Q001111zzLMmmmm0110H0nnnnnddddd")
|
||||||
|
//INST(SQDMLSL_elt_2, "SQDMLSL, SQDMLSL2 (by element)", "0Q001111zzLMmmmm0111H0nnnnnddddd")
|
||||||
//INST(MUL_elt, "MUL (by element)", "0Q001111zzLMmmmm1000H0nnnnnddddd")
|
//INST(MUL_elt, "MUL (by element)", "0Q001111zzLMmmmm1000H0nnnnnddddd")
|
||||||
//INST(SMULL_elt, "SMULL, SMULL2 (by element)", "0Q001111zzLMmmmm1010H0nnnnnddddd")
|
//INST(SMULL_elt, "SMULL, SMULL2 (by element)", "0Q001111zzLMmmmm1010H0nnnnnddddd")
|
||||||
|
//INST(SQDMULL_elt_2, "SQDMULL, SQDMULL2 (by element)", "0Q001111zzLMmmmm1011H0nnnnnddddd")
|
||||||
|
//INST(SQDMULH_elt_2, "SQDMULH (by element)", "0Q001111zzLMmmmm1100H0nnnnnddddd")
|
||||||
|
//INST(SQRDMULH_elt_2, "SQRDMULH (by element)", "0Q001111zzLMmmmm1101H0nnnnnddddd")
|
||||||
//INST(SDOT_elt, "SDOT (by element)", "0Q001111zzLMmmmm1110H0nnnnnddddd")
|
//INST(SDOT_elt, "SDOT (by element)", "0Q001111zzLMmmmm1110H0nnnnnddddd")
|
||||||
|
//INST(FMLA_elt_3, "FMLA (by element)", "0Q00111100LMmmmm0001H0nnnnnddddd")
|
||||||
|
//INST(FMLA_elt_4, "FMLA (by element)", "0Q0011111zLMmmmm0001H0nnnnnddddd")
|
||||||
|
//INST(FMLS_elt_3, "FMLS (by element)", "0Q00111100LMmmmm0101H0nnnnnddddd")
|
||||||
|
//INST(FMLS_elt_4, "FMLS (by element)", "0Q0011111zLMmmmm0101H0nnnnnddddd")
|
||||||
|
//INST(FMUL_elt_3, "FMUL (by element)", "0Q00111100LMmmmm1001H0nnnnnddddd")
|
||||||
|
//INST(FMUL_elt_4, "FMUL (by element)", "0Q0011111zLMmmmm1001H0nnnnnddddd")
|
||||||
//INST(FMLAL_elt_1, "FMLAL, FMLAL2 (by element)", "0Q0011111zLMmmmm0000H0nnnnnddddd")
|
//INST(FMLAL_elt_1, "FMLAL, FMLAL2 (by element)", "0Q0011111zLMmmmm0000H0nnnnnddddd")
|
||||||
//INST(FMLAL_elt_2, "FMLAL, FMLAL2 (by element)", "0Q1011111zLMmmmm1000H0nnnnnddddd")
|
//INST(FMLAL_elt_2, "FMLAL, FMLAL2 (by element)", "0Q1011111zLMmmmm1000H0nnnnnddddd")
|
||||||
//INST(FMLSL_elt_1, "FMLSL, FMLSL2 (by element)", "0Q0011111zLMmmmm0100H0nnnnnddddd")
|
//INST(FMLSL_elt_1, "FMLSL, FMLSL2 (by element)", "0Q0011111zLMmmmm0100H0nnnnnddddd")
|
||||||
|
|
@ -841,7 +837,11 @@ INST(EOR_asimd, "EOR (vector)", "0Q101
|
||||||
//INST(MLS_elt, "MLS (by element)", "0Q101111zzLMmmmm0100H0nnnnnddddd")
|
//INST(MLS_elt, "MLS (by element)", "0Q101111zzLMmmmm0100H0nnnnnddddd")
|
||||||
//INST(UMLSL_elt, "UMLSL, UMLSL2 (by element)", "0Q101111zzLMmmmm0110H0nnnnnddddd")
|
//INST(UMLSL_elt, "UMLSL, UMLSL2 (by element)", "0Q101111zzLMmmmm0110H0nnnnnddddd")
|
||||||
//INST(UMULL_elt, "UMULL, UMULL2 (by element)", "0Q101111zzLMmmmm1010H0nnnnnddddd")
|
//INST(UMULL_elt, "UMULL, UMULL2 (by element)", "0Q101111zzLMmmmm1010H0nnnnnddddd")
|
||||||
|
//INST(SQRDMLAH_elt_2, "SQRDMLAH (by element)", "0Q101111zzLMmmmm1101H0nnnnnddddd")
|
||||||
//INST(UDOT_elt, "UDOT (by element)", "0Q101111zzLMmmmm1110H0nnnnnddddd")
|
//INST(UDOT_elt, "UDOT (by element)", "0Q101111zzLMmmmm1110H0nnnnnddddd")
|
||||||
|
//INST(SQRDMLSH_elt_2, "SQRDMLSH (by element)", "0Q101111zzLMmmmm1111H0nnnnnddddd")
|
||||||
|
//INST(FMULX_elt_3, "FMULX (by element)", "0Q10111100LMmmmm1001H0nnnnnddddd")
|
||||||
|
//INST(FMULX_elt_4, "FMULX (by element)", "0Q1011111zLMmmmm1001H0nnnnnddddd")
|
||||||
//INST(FCMLA_elt, "FCMLA (by element)", "0Q101111zzLMmmmm0rr1H0nnnnnddddd")
|
//INST(FCMLA_elt, "FCMLA (by element)", "0Q101111zzLMmmmm0rr1H0nnnnnddddd")
|
||||||
|
|
||||||
// Data Processing - FP and SIMD - Cryptographic three register
|
// Data Processing - FP and SIMD - Cryptographic three register
|
||||||
|
|
|
||||||
|
|
@ -34,51 +34,6 @@ bool TranslatorVisitor::ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd)
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool TranslatorVisitor::BIC_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
|
||||||
const size_t datasize = Q ? 128 : 64;
|
|
||||||
|
|
||||||
const IR::U128 operand1 = V(datasize, Vn);
|
|
||||||
const IR::U128 operand2 = V(datasize, Vm);
|
|
||||||
|
|
||||||
IR::U128 result = ir.VectorAnd(operand1, ir.VectorNot(operand2));
|
|
||||||
if (datasize == 64) {
|
|
||||||
result = ir.VectorZeroUpper(result);
|
|
||||||
}
|
|
||||||
|
|
||||||
V(datasize, Vd, result);
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
bool TranslatorVisitor::CMEQ_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
||||||
if (size == 0b11 && !Q) return ReservedValue();
|
|
||||||
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
|
||||||
const size_t datasize = Q ? 128 : 64;
|
|
||||||
|
|
||||||
const IR::U128 operand1 = V(datasize, Vn);
|
|
||||||
const IR::U128 operand2 = V(datasize, Vm);
|
|
||||||
|
|
||||||
IR::U128 result = [&]{
|
|
||||||
switch (esize) {
|
|
||||||
case 8:
|
|
||||||
return ir.VectorEqual8(operand1, operand2);
|
|
||||||
case 16:
|
|
||||||
return ir.VectorEqual16(operand1, operand2);
|
|
||||||
case 32:
|
|
||||||
return ir.VectorEqual32(operand1, operand2);
|
|
||||||
default:
|
|
||||||
return ir.VectorEqual64(operand1, operand2);
|
|
||||||
}
|
|
||||||
}();
|
|
||||||
|
|
||||||
if (datasize == 64) {
|
|
||||||
result = ir.VectorZeroUpper(result);
|
|
||||||
}
|
|
||||||
|
|
||||||
V(datasize, Vd, result);
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
||||||
if (size == 0b11 && !Q) return ReservedValue();
|
if (size == 0b11 && !Q) return ReservedValue();
|
||||||
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
||||||
|
|
@ -118,6 +73,21 @@ bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool TranslatorVisitor::BIC_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
||||||
|
const size_t datasize = Q ? 128 : 64;
|
||||||
|
|
||||||
|
const IR::U128 operand1 = V(datasize, Vn);
|
||||||
|
const IR::U128 operand2 = V(datasize, Vm);
|
||||||
|
|
||||||
|
IR::U128 result = ir.VectorAnd(operand1, ir.VectorNot(operand2));
|
||||||
|
if (datasize == 64) {
|
||||||
|
result = ir.VectorZeroUpper(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
V(datasize, Vd, result);
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
bool TranslatorVisitor::ORR_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
bool TranslatorVisitor::ORR_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
||||||
const size_t datasize = Q ? 128 : 64;
|
const size_t datasize = Q ? 128 : 64;
|
||||||
|
|
||||||
|
|
@ -148,6 +118,36 @@ bool TranslatorVisitor::ORN_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool TranslatorVisitor::CMEQ_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
||||||
|
if (size == 0b11 && !Q) return ReservedValue();
|
||||||
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
||||||
|
const size_t datasize = Q ? 128 : 64;
|
||||||
|
|
||||||
|
const IR::U128 operand1 = V(datasize, Vn);
|
||||||
|
const IR::U128 operand2 = V(datasize, Vm);
|
||||||
|
|
||||||
|
IR::U128 result = [&]{
|
||||||
|
switch (esize) {
|
||||||
|
case 8:
|
||||||
|
return ir.VectorEqual8(operand1, operand2);
|
||||||
|
case 16:
|
||||||
|
return ir.VectorEqual16(operand1, operand2);
|
||||||
|
case 32:
|
||||||
|
return ir.VectorEqual32(operand1, operand2);
|
||||||
|
default:
|
||||||
|
return ir.VectorEqual64(operand1, operand2);
|
||||||
|
}
|
||||||
|
}();
|
||||||
|
|
||||||
|
if (datasize == 64) {
|
||||||
|
result = ir.VectorZeroUpper(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
V(datasize, Vd, result);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
bool TranslatorVisitor::EOR_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
bool TranslatorVisitor::EOR_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
||||||
const size_t datasize = Q ? 128 : 64;
|
const size_t datasize = Q ? 128 : 64;
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue