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emit_arm64_data_processing: Deal with pseudo-op use issue

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See #728
This commit is contained in:
Merry 2022-11-30 00:30:33 +00:00
parent 8f9838e9b0
commit 2d3c8c5724
2 changed files with 6 additions and 6 deletions
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9
src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
View file

@ -269,8 +269,8 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(oaknut::CodeGenerator& code, EmitCon
} }
} else { } else {
if (shift_arg.IsImmediate() && shift_arg.GetImmediateU8() == 0) { if (shift_arg.IsImmediate() && shift_arg.GetImmediateU8() == 0) {
ctx.reg_alloc.DefineAsExisting(inst, operand_arg);
ctx.reg_alloc.DefineAsExisting(carry_inst, carry_arg); ctx.reg_alloc.DefineAsExisting(carry_inst, carry_arg);
ctx.reg_alloc.DefineAsExisting(inst, operand_arg);
} else if (shift_arg.IsImmediate()) { } else if (shift_arg.IsImmediate()) {
// TODO: Use RMIF // TODO: Use RMIF
const u8 shift = shift_arg.GetImmediateU8(); const u8 shift = shift_arg.GetImmediateU8();
@ -406,8 +406,8 @@ void EmitIR<IR::Opcode::LogicalShiftRight32>(oaknut::CodeGenerator& code, EmitCo
} }
} else { } else {
if (shift_arg.IsImmediate() && shift_arg.GetImmediateU8() == 0) { if (shift_arg.IsImmediate() && shift_arg.GetImmediateU8() == 0) {
ctx.reg_alloc.DefineAsExisting(inst, operand_arg);
ctx.reg_alloc.DefineAsExisting(carry_inst, carry_arg); ctx.reg_alloc.DefineAsExisting(carry_inst, carry_arg);
ctx.reg_alloc.DefineAsExisting(inst, operand_arg);
} else if (shift_arg.IsImmediate()) { } else if (shift_arg.IsImmediate()) {
// TODO: Use RMIF // TODO: Use RMIF
const u8 shift = shift_arg.GetImmediateU8(); const u8 shift = shift_arg.GetImmediateU8();
@ -541,8 +541,8 @@ void EmitIR<IR::Opcode::ArithmeticShiftRight32>(oaknut::CodeGenerator& code, Emi
} }
} else { } else {
if (shift_arg.IsImmediate() && shift_arg.GetImmediateU8() == 0) { if (shift_arg.IsImmediate() && shift_arg.GetImmediateU8() == 0) {
ctx.reg_alloc.DefineAsExisting(inst, operand_arg);
ctx.reg_alloc.DefineAsExisting(carry_inst, carry_arg); ctx.reg_alloc.DefineAsExisting(carry_inst, carry_arg);
ctx.reg_alloc.DefineAsExisting(inst, operand_arg);
} else if (shift_arg.IsImmediate()) { } else if (shift_arg.IsImmediate()) {
// TODO: Use RMIF // TODO: Use RMIF
@ -632,11 +632,10 @@ void EmitIR<IR::Opcode::RotateRight32>(oaknut::CodeGenerator& code, EmitContext&
auto& carry_arg = args[2]; auto& carry_arg = args[2];
if (shift_arg.IsImmediate() && shift_arg.GetImmediateU8() == 0) { if (shift_arg.IsImmediate() && shift_arg.GetImmediateU8() == 0) {
ctx.reg_alloc.DefineAsExisting(inst, operand_arg);
if (carry_inst) { if (carry_inst) {
ctx.reg_alloc.DefineAsExisting(carry_inst, carry_arg); ctx.reg_alloc.DefineAsExisting(carry_inst, carry_arg);
} }
ctx.reg_alloc.DefineAsExisting(inst, operand_arg);
} else if (shift_arg.IsImmediate()) { } else if (shift_arg.IsImmediate()) {
const u8 shift = shift_arg.GetImmediateU8() % 32; const u8 shift = shift_arg.GetImmediateU8() % 32;
auto Wresult = ctx.reg_alloc.WriteW(inst); auto Wresult = ctx.reg_alloc.WriteW(inst);

3
src/dynarmic/backend/arm64/reg_alloc.cpp
View file

@ -170,12 +170,13 @@ void RegAlloc::PrepareForCall(IR::Inst* result, std::optional<Argument::copyable
} }
void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) { void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
ASSERT(!ValueLocation(inst));
if (arg.value.IsImmediate()) { if (arg.value.IsImmediate()) {
inst->ReplaceUsesWith(arg.value); inst->ReplaceUsesWith(arg.value);
return; return;
} }
ASSERT(!ValueLocation(inst));
auto& info = ValueInfo(arg.value.GetInst()); auto& info = ValueInfo(arg.value.GetInst());
info.values.emplace_back(inst); info.values.emplace_back(inst);
info.expected_uses += inst->UseCount(); info.expected_uses += inst->UseCount();