a32_jitstate: Consolidate upper bits of location descriptor into upper_location_descriptor
Also solves a performance regression initially introduced by b6e8297e369f2dc4758bafe944e51efb8d1a2552, primarily due to excessively mismatched load/store sizes causing less than optimal load-to-store forwarding.
This commit is contained in:
MerryMage
parent
e41a7dc678
commit
2f2a859615
5 changed files with 86 additions and 97 deletions
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@ -219,11 +219,11 @@ void A32EmitX64::GenTerminalHandlers() {
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// location_descriptor ends up in rbx
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const auto calculate_location_descriptor = [this] {
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// This calculation has to match up with IREmitter::PushRSB
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constexpr size_t offsetof_pc = offsetof(A32JitState, Reg) + 15 * sizeof(u32);
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static_assert(offsetof_pc + 4 == offsetof(A32JitState, cpsr_et));
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static_assert(offsetof_pc + 5 == offsetof(A32JitState, cpsr_it));
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static_assert(offsetof_pc + 6 == offsetof(A32JitState, fpcr_mode));
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code.mov(rbx, qword[r15 + offsetof_pc]);
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code.mov(ebx, dword[r15 + offsetof(A32JitState, upper_location_descriptor)]);
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code.shl(rbx, 32);
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code.mov(ecx, MJitStateReg(A32::Reg::PC));
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code.mov(ebp, ecx);
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code.or_(rbx, rcx);
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};
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Xbyak::Label fast_dispatch_cache_miss, rsb_cache_miss;
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@ -347,16 +347,18 @@ void A32EmitX64::EmitA32GetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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code.mov(result, dword[r15 + offsetof(A32JitState, cpsr_ge)]);
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code.mov(tmp, 0x80808080);
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code.pext(result, result, tmp);
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code.shr(result, 16);
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// Here we observe that cpsr_et and cpsr_ge are right next to each other in memory,
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// so we load them both at the same time with one 64-bit read. This allows us to
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// extract all of their bits together at once with one pext.
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static_assert(offsetof(A32JitState, upper_location_descriptor) + 4 == offsetof(A32JitState, cpsr_ge));
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code.mov(result.cvt64(), qword[r15 + offsetof(A32JitState, upper_location_descriptor)]);
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code.mov(tmp.cvt64(), 0x80808080'00000003ull);
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code.pext(result.cvt64(), result.cvt64(), tmp.cvt64());
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code.mov(tmp, 0x000f0220);
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code.pdep(result, result, tmp);
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code.mov(tmp, dword[r15 + offsetof(A32JitState, cpsr_q)]);
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code.shl(tmp, 27);
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code.or_(result, tmp);
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code.movzx(tmp, code.byte[r15 + offsetof(A32JitState, cpsr_et)]);
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code.shl(tmp, 5);
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code.or_(result, tmp);
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code.or_(result, dword[r15 + offsetof(A32JitState, cpsr_nzcv)]);
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code.or_(result, dword[r15 + offsetof(A32JitState, cpsr_jaifm)]);
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@ -378,6 +380,7 @@ void A32EmitX64::EmitA32SetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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const Xbyak::Reg32 cpsr = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 tmp2 = ctx.reg_alloc.ScratchGpr().cvt32();
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// cpsr_q
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code.bt(cpsr, 27);
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@ -393,21 +396,19 @@ void A32EmitX64::EmitA32SetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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code.and_(tmp, 0x07F0FDDF);
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_jaifm)], tmp);
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// cpsr_et
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code.mov(tmp, cpsr);
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code.shr(tmp, 5);
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code.and_(tmp, 0x11);
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code.mov(code.byte[r15 + offsetof(A32JitState, cpsr_et)], tmp.cvt8());
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// cpsr_ge
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code.shr(cpsr, 16);
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code.mov(tmp, 0x01010101);
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code.pdep(cpsr, cpsr, tmp);
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// cpsr_et and cpsr_ge
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static_assert(offsetof(A32JitState, upper_location_descriptor) + 4 == offsetof(A32JitState, cpsr_ge));
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code.and_(qword[r15 + offsetof(A32JitState, upper_location_descriptor)], u32(0xFFFF0000));
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code.mov(tmp, 0x000f0220);
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code.pext(cpsr, cpsr, tmp);
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code.mov(tmp.cvt64(), 0x01010101'00000003ull);
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code.pdep(cpsr.cvt64(), cpsr.cvt64(), tmp.cvt64());
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// We perform SWAR partitioned subtraction here, to negate the GE bytes.
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code.mov(tmp, 0x80808080);
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code.sub(tmp, cpsr);
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code.xor_(tmp, 0x80808080);
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_ge)], tmp);
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code.mov(tmp.cvt64(), 0x80808080'00000003ull);
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code.mov(tmp2.cvt64(), tmp.cvt64());
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code.sub(tmp.cvt64(), cpsr.cvt64());
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code.xor_(tmp.cvt64(), tmp2.cvt64());
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code.or_(qword[r15 + offsetof(A32JitState, upper_location_descriptor)], tmp.cvt64());
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} else {
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ctx.reg_alloc.HostCall(nullptr, args[0]);
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code.mov(code.ABI_PARAM2, code.r15);
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@ -644,6 +645,8 @@ void A32EmitX64::EmitA32BXWritePC(A32EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto& arg = args[0];
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const u32 upper_without_t = (ctx.Location().UniqueHash() >> 32) & 0xFFFFFFFE;
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// Pseudocode:
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// if (new_pc & 1) {
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// new_pc &= 0xFFFFFFFE;
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@ -657,36 +660,22 @@ void A32EmitX64::EmitA32BXWritePC(A32EmitContext& ctx, IR::Inst* inst) {
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if (arg.IsImmediate()) {
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const u32 new_pc = arg.GetImmediateU32();
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const u32 mask = Common::Bit<0>(new_pc) ? 0xFFFFFFFE : 0xFFFFFFFC;
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u32 et = 0;
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et |= ctx.Location().EFlag() ? 0x10 : 0;
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et |= Common::Bit<0>(new_pc) ? 0x01 : 0;
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const u32 new_upper = upper_without_t | (Common::Bit<0>(new_pc) ? 1 : 0);
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code.mov(MJitStateReg(A32::Reg::PC), new_pc & mask);
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code.mov(code.byte[r15 + offsetof(A32JitState, cpsr_et)], u8(et));
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} else {
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if (ctx.Location().EFlag()) {
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const Xbyak::Reg32 new_pc = ctx.reg_alloc.UseScratchGpr(arg).cvt32();
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const Xbyak::Reg32 mask = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 et = ctx.reg_alloc.ScratchGpr().cvt32();
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code.mov(mask, new_pc);
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code.and_(mask, 1);
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code.lea(et, ptr[mask.cvt64() + 0x10]);
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code.mov(code.byte[r15 + offsetof(A32JitState, cpsr_et)], et.cvt8());
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code.lea(mask, ptr[mask.cvt64() + mask.cvt64() * 1 - 4]); // mask = pc & 1 ? 0xFFFFFFFE : 0xFFFFFFFC
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code.and_(new_pc, mask);
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code.mov(MJitStateReg(A32::Reg::PC), new_pc);
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code.mov(dword[r15 + offsetof(A32JitState, upper_location_descriptor)], new_upper);
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} else {
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const Xbyak::Reg32 new_pc = ctx.reg_alloc.UseScratchGpr(arg).cvt32();
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const Xbyak::Reg32 mask = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 new_upper = ctx.reg_alloc.ScratchGpr().cvt32();
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code.mov(mask, new_pc);
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code.and_(mask, 1);
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code.mov(code.byte[r15 + offsetof(A32JitState, cpsr_et)], mask.cvt8());
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code.lea(new_upper, ptr[mask.cvt64() + upper_without_t]);
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code.lea(mask, ptr[mask.cvt64() + mask.cvt64() * 1 - 4]); // mask = pc & 1 ? 0xFFFFFFFE : 0xFFFFFFFC
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code.and_(new_pc, mask);
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code.mov(MJitStateReg(A32::Reg::PC), new_pc);
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}
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code.mov(dword[r15 + offsetof(A32JitState, upper_location_descriptor)], new_upper);
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}
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}
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@ -1259,17 +1248,13 @@ void A32EmitX64::EmitTerminalImpl(IR::Term::ReturnToDispatch, IR::LocationDescri
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code.ReturnFromRunCode();
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}
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static u8 CalculateCpsr_et(const IR::LocationDescriptor& arg) {
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const A32::LocationDescriptor desc{arg};
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u8 et = 0;
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et |= desc.EFlag() ? 0x10 : 0;
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et |= desc.TFlag() ? 0x01 : 0;
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return et;
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static u32 CalculateUpper(const IR::LocationDescriptor& arg) {
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return static_cast<u32>(arg.Value() >> 32);
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}
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void A32EmitX64::EmitTerminalImpl(IR::Term::LinkBlock terminal, IR::LocationDescriptor initial_location) {
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if (CalculateCpsr_et(terminal.next) != CalculateCpsr_et(initial_location)) {
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code.mov(code.byte[r15 + offsetof(A32JitState, cpsr_et)], CalculateCpsr_et(terminal.next));
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if (CalculateUpper(terminal.next) != CalculateUpper(initial_location)) {
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code.mov(dword[r15 + offsetof(A32JitState, upper_location_descriptor)], CalculateUpper(terminal.next));
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}
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code.cmp(qword[r15 + offsetof(A32JitState, cycles_remaining)], 0);
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@ -1293,8 +1278,8 @@ void A32EmitX64::EmitTerminalImpl(IR::Term::LinkBlock terminal, IR::LocationDesc
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}
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void A32EmitX64::EmitTerminalImpl(IR::Term::LinkBlockFast terminal, IR::LocationDescriptor initial_location) {
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if (CalculateCpsr_et(terminal.next) != CalculateCpsr_et(initial_location)) {
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code.mov(code.byte[r15 + offsetof(A32JitState, cpsr_et)], CalculateCpsr_et(terminal.next));
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if (CalculateUpper(terminal.next) != CalculateUpper(initial_location)) {
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code.mov(dword[r15 + offsetof(A32JitState, upper_location_descriptor)], CalculateUpper(terminal.next));
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}
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patch_information[terminal.next].jmp.emplace_back(code.getCurr());
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@ -115,7 +115,7 @@ private:
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u32 pc = jit_state.Reg[15];
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A32::PSR cpsr{jit_state.Cpsr()};
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A32::FPSCR fpscr{jit_state.fpcr_mode};
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A32::FPSCR fpscr{jit_state.upper_location_descriptor};
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A32::LocationDescriptor descriptor{pc, cpsr, fpscr};
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return this_.GetBasicBlock(descriptor).entrypoint;
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@ -46,10 +46,9 @@ namespace Dynarmic::BackendX64 {
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*/
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u32 A32JitState::Cpsr() const {
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ASSERT((cpsr_nzcv & ~0xF0000000) == 0);
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ASSERT((cpsr_q & ~1) == 0);
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ASSERT((cpsr_et & ~0x11) == 0);
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ASSERT((cpsr_jaifm & ~0x010001DF) == 0);
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DEBUG_ASSERT((cpsr_nzcv & ~0xF0000000) == 0);
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DEBUG_ASSERT((cpsr_q & ~1) == 0);
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DEBUG_ASSERT((cpsr_jaifm & ~0x010001DF) == 0);
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u32 cpsr = 0;
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@ -63,10 +62,11 @@ u32 A32JitState::Cpsr() const {
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cpsr |= Common::Bit<15>(cpsr_ge) ? 1 << 17 : 0;
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cpsr |= Common::Bit<7>(cpsr_ge) ? 1 << 16 : 0;
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// E flag, T flag
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cpsr |= static_cast<u32>(cpsr_et) << 5;
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cpsr |= Common::Bit<1>(upper_location_descriptor) ? 1 << 9 : 0;
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cpsr |= Common::Bit<0>(upper_location_descriptor) ? 1 << 5 : 0;
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// IT state
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cpsr |= static_cast<u32>(cpsr_it & 0b11111100) << 8;
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cpsr |= static_cast<u32>(cpsr_it & 0b00000011) << 25;
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cpsr |= static_cast<u32>(upper_location_descriptor & 0b11111100'00000000);
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cpsr |= static_cast<u32>(upper_location_descriptor & 0b00000011'00000000) << 17;
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// Other flags
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cpsr |= cpsr_jaifm;
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@ -84,12 +84,15 @@ void A32JitState::SetCpsr(u32 cpsr) {
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cpsr_ge |= Common::Bit<18>(cpsr) ? 0x00FF0000 : 0;
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cpsr_ge |= Common::Bit<17>(cpsr) ? 0x0000FF00 : 0;
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cpsr_ge |= Common::Bit<16>(cpsr) ? 0x000000FF : 0;
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upper_location_descriptor &= 0xFFFF0000;
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// E flag, T flag
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cpsr_et = static_cast<u8>((cpsr >> 5) & 0x11);
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upper_location_descriptor |= Common::Bit<9>(cpsr) ? 2 : 0;
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upper_location_descriptor |= Common::Bit<5>(cpsr) ? 1 : 0;
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// IT state
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cpsr_it = 0;
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cpsr_it |= static_cast<u8>((cpsr >> 8) & 0b11111100);
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cpsr_it |= static_cast<u8>((cpsr >> 25) & 0b00000011);
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upper_location_descriptor |= (cpsr >> 0) & 0b11111100'00000000;
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upper_location_descriptor |= (cpsr >> 17) & 0b00000011'00000000;
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// Other flags
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cpsr_jaifm = cpsr & 0x010001DF;
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}
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@ -160,12 +163,11 @@ constexpr u32 FPSCR_MODE_MASK = A32::LocationDescriptor::FPSCR_MODE_MASK;
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constexpr u32 FPSCR_NZCV_MASK = 0xF0000000;
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u32 A32JitState::Fpscr() const {
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const u32 fpcr_mode_shifted = static_cast<u32>(fpcr_mode) << 16;
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DEBUG_ASSERT((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0);
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ASSERT((fpcr_mode_shifted & ~FPSCR_MODE_MASK) == 0);
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ASSERT((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0);
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const u32 fpcr_mode = static_cast<u32>(upper_location_descriptor) & FPSCR_MODE_MASK;
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u32 FPSCR = fpcr_mode_shifted | fpsr_nzcv;
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u32 FPSCR = fpcr_mode | fpsr_nzcv;
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FPSCR |= (guest_MXCSR & 0b0000000000001); // IOC = IE
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FPSCR |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
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FPSCR |= fpsr_exc;
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@ -174,7 +176,12 @@ u32 A32JitState::Fpscr() const {
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}
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void A32JitState::SetFpscr(u32 FPSCR) {
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fpcr_mode = static_cast<u16>((FPSCR & FPSCR_MODE_MASK) >> 16);
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// Ensure that only upper half of upper_location_descriptor is used for FPSCR bits.
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static_assert((FPSCR_MODE_MASK & 0xFFFF0000) == FPSCR_MODE_MASK);
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upper_location_descriptor &= 0x0000FFFF;
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upper_location_descriptor |= FPSCR & FPSCR_MODE_MASK;
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fpsr_nzcv = FPSCR & FPSCR_NZCV_MASK;
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guest_MXCSR = 0;
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@ -29,16 +29,8 @@ struct A32JitState {
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std::array<u32, 16> Reg{}; // Current register file.
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// TODO: Mode-specific register sets unimplemented.
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// Location Descriptor related (the order of fields is important)
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u8 cpsr_et = 0; ///< Format: 000E000T
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u8 cpsr_it = 0; ///< Format: ccccmmmm
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u16 fpcr_mode = 0; ///< Top 16 bits of FPCR
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u64 GetUniqueHash() const noexcept {
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const u64 upper_half = u64(cpsr_et) | (u64(cpsr_it) << 8) | (u64(fpcr_mode) << 16);
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return (upper_half << 32) | Reg[15];
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}
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u32 upper_location_descriptor = 0;
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// CPSR fields
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u32 cpsr_ge = 0;
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u32 cpsr_q = 0;
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u32 cpsr_nzcv = 0;
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@ -80,6 +72,10 @@ struct A32JitState {
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u32 fpsr_nzcv = 0;
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u32 Fpscr() const;
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void SetFpscr(u32 FPSCR);
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u64 GetUniqueHash() const noexcept {
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return (static_cast<u64>(upper_location_descriptor) << 32) | (static_cast<u64>(Reg[15]));
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}
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};
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#ifdef _MSC_VER
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@ -34,10 +34,10 @@ public:
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explicit LocationDescriptor(const IR::LocationDescriptor& o) {
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arm_pc = static_cast<u32>(o.Value());
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cpsr.T(o.Value() & (u64(0x01) << 32));
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cpsr.E(o.Value() & (u64(0x10) << 32));
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cpsr.T((o.Value() >> 32) & 1);
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cpsr.E((o.Value() >> 32) & 2);
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fpscr = (o.Value() >> 32) & FPSCR_MODE_MASK;
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cpsr.IT(ITState{static_cast<u8>(o.Value() >> 40)});
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fpscr = static_cast<u32>(o.Value() >> 32) & FPSCR_MODE_MASK;
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}
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u32 PC() const { return arm_pc; }
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@ -92,12 +92,13 @@ public:
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u64 UniqueHash() const noexcept {
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// This value MUST BE UNIQUE.
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// This calculation has to match up with EmitX64::EmitTerminalPopRSBHint
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const u64 pc_u64 = u64(arm_pc);
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const u64 fpscr_u64 = u64(fpscr.Value()) << 32;
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const u64 it_u64 = u64(cpsr.IT().Value()) << 40;
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const u64 t_u64 = cpsr.T() ? u64(0x01) << 32 : 0;
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const u64 e_u64 = cpsr.E() ? u64(0x10) << 32 : 0;
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return pc_u64 | fpscr_u64 | it_u64 | t_u64 | e_u64;
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const u64 pc_u64 = arm_pc;
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const u64 fpscr_u64 = fpscr.Value();
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const u64 t_u64 = cpsr.T() ? 1 : 0;
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const u64 e_u64 = cpsr.E() ? 2 : 0;
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const u64 it_u64 = u64(cpsr.IT().Value()) << 8;
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const u64 upper = (fpscr_u64 | t_u64 | e_u64 | it_u64) << 32;
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return pc_u64 | upper;
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}
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operator IR::LocationDescriptor() const {
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Reference in a new issue