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Merge pull request #492 from lioncash/vfp

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A32: Rename vfp2-related files to vfp
This commit is contained in:
Merry 2019-05-02 23:46:53 +01:00 committed by MerryMage
commit 30d28029a8
9 changed files with 174 additions and 174 deletions
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6
src/CMakeLists.txt
View file

@ -82,8 +82,8 @@ add_library(dynarmic
frontend/A32/decoder/arm.inc frontend/A32/decoder/arm.inc
frontend/A32/decoder/thumb16.h frontend/A32/decoder/thumb16.h
frontend/A32/decoder/thumb32.h frontend/A32/decoder/thumb32.h
frontend/A32/decoder/vfp2.h frontend/A32/decoder/vfp.h
frontend/A32/decoder/vfp2.inc frontend/A32/decoder/vfp.inc
frontend/A32/disassembler/disassembler.h frontend/A32/disassembler/disassembler.h
frontend/A32/disassembler/disassembler_arm.cpp frontend/A32/disassembler/disassembler_arm.cpp
frontend/A32/disassembler/disassembler_thumb.cpp frontend/A32/disassembler/disassembler_thumb.cpp
@ -115,7 +115,7 @@ add_library(dynarmic
frontend/A32/translate/translate_arm/status_register_access.cpp frontend/A32/translate/translate_arm/status_register_access.cpp
frontend/A32/translate/translate_arm/synchronization.cpp frontend/A32/translate/translate_arm/synchronization.cpp
frontend/A32/translate/translate_arm/translate_arm.h frontend/A32/translate/translate_arm/translate_arm.h
frontend/A32/translate/translate_arm/vfp2.cpp frontend/A32/translate/translate_arm/vfp.cpp
frontend/A32/translate/translate_thumb.cpp frontend/A32/translate/translate_thumb.cpp
frontend/A32/types.cpp frontend/A32/types.cpp
frontend/A32/types.h frontend/A32/types.h

12
src/frontend/A32/decoder/vfp2.h → src/frontend/A32/decoder/vfp.h
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@ -19,14 +19,14 @@
namespace Dynarmic::A32 { namespace Dynarmic::A32 {
template <typename Visitor> template <typename Visitor>
using VFP2Matcher = Decoder::Matcher<Visitor, u32>; using VFPMatcher = Decoder::Matcher<Visitor, u32>;
template<typename V> template<typename V>
std::optional<std::reference_wrapper<const VFP2Matcher<V>>> DecodeVFP2(u32 instruction) { std::optional<std::reference_wrapper<const VFPMatcher<V>>> DecodeVFP(u32 instruction) {
static const std::vector<VFP2Matcher<V>> table = { static const std::vector<VFPMatcher<V>> table = {
#define INST(fn, name, bitstring) Decoder::detail::detail<VFP2Matcher<V>>::GetMatcher(&V::fn, name, bitstring), #define INST(fn, name, bitstring) Decoder::detail::detail<VFPMatcher<V>>::GetMatcher(&V::fn, name, bitstring),
#include "vfp2.inc" #include "vfp.inc"
#undef INST #undef INST
}; };
@ -37,7 +37,7 @@ std::optional<std::reference_wrapper<const VFP2Matcher<V>>> DecodeVFP2(u32 instr
const auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); }; const auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); };
auto iter = std::find_if(table.begin(), table.end(), matches_instruction); auto iter = std::find_if(table.begin(), table.end(), matches_instruction);
return iter != table.end() ? std::optional<std::reference_wrapper<const VFP2Matcher<V>>>(*iter) : std::nullopt; return iter != table.end() ? std::optional<std::reference_wrapper<const VFPMatcher<V>>>(*iter) : std::nullopt;
} }
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

48
src/frontend/A32/decoder/vfp.inc Normal file
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@ -0,0 +1,48 @@
// cccc1110________----101-__-0----
// Floating-point three-register data processing instructions
INST(vfp_VMLA, "VMLA", "cccc11100D00nnnndddd101zN0M0mmmm") // VFPv2
INST(vfp_VMLS, "VMLS", "cccc11100D00nnnndddd101zN1M0mmmm") // VFPv2
INST(vfp_VNMLS, "VNMLS", "cccc11100D01nnnndddd101zN0M0mmmm") // VFPv2
INST(vfp_VNMLA, "VNMLA", "cccc11100D01nnnndddd101zN1M0mmmm") // VFPv2
INST(vfp_VMUL, "VMUL", "cccc11100D10nnnndddd101zN0M0mmmm") // VFPv2
INST(vfp_VNMUL, "VNMUL", "cccc11100D10nnnndddd101zN1M0mmmm") // VFPv2
INST(vfp_VADD, "VADD", "cccc11100D11nnnndddd101zN0M0mmmm") // VFPv2
INST(vfp_VSUB, "VSUB", "cccc11100D11nnnndddd101zN1M0mmmm") // VFPv2
INST(vfp_VDIV, "VDIV", "cccc11101D00nnnndddd101zN0M0mmmm") // VFPv2
// Floating-point move instructions
INST(vfp_VMOV_u32_f64, "VMOV (core to f64)", "cccc11100000ddddtttt1011D0010000") // VFPv2
INST(vfp_VMOV_f64_u32, "VMOV (f64 to core)", "cccc11100001nnnntttt1011N0010000") // VFPv2
INST(vfp_VMOV_u32_f32, "VMOV (core to f32)", "cccc11100000nnnntttt1010N0010000") // VFPv2
INST(vfp_VMOV_f32_u32, "VMOV (f32 to core)", "cccc11100001nnnntttt1010N0010000") // VFPv2
INST(vfp_VMOV_2u32_2f32, "VMOV (2xcore to 2xf32)", "cccc11000100uuuutttt101000M1mmmm") // VFPv2
INST(vfp_VMOV_2f32_2u32, "VMOV (2xf32 to 2xcore)", "cccc11000101uuuutttt101000M1mmmm") // VFPv2
INST(vfp_VMOV_2u32_f64, "VMOV (2xcore to f64)", "cccc11000100uuuutttt101100M1mmmm") // VFPv2
INST(vfp_VMOV_f64_2u32, "VMOV (f64 to 2xcore)", "cccc11000101uuuutttt101100M1mmmm") // VFPv2
INST(vfp_VMOV_reg, "VMOV (reg)", "cccc11101D110000dddd101z01M0mmmm") // VFPv2
// Floating-point other instructions
INST(vfp_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm") // VFPv2
INST(vfp_VNEG, "VNEG", "cccc11101D110001dddd101z01M0mmmm") // VFPv2
INST(vfp_VSQRT, "VSQRT", "cccc11101D110001dddd101z11M0mmmm") // VFPv2
INST(vfp_VCVT_f_to_f, "VCVT (f32<->f64)", "cccc11101D110111dddd101z11M0mmmm") // VFPv2
INST(vfp_VCVT_to_float, "VCVT (to float)", "cccc11101D111000dddd101zs1M0mmmm") // VFPv2
INST(vfp_VCVT_to_u32, "VCVT (to u32)", "cccc11101D111100dddd101zr1M0mmmm") // VFPv2
INST(vfp_VCVT_to_s32, "VCVT (to s32)", "cccc11101D111101dddd101zr1M0mmmm") // VFPv2
INST(vfp_VCMP, "VCMP", "cccc11101D110100dddd101zE1M0mmmm") // VFPv2
INST(vfp_VCMP_zero, "VCMP (with zero)", "cccc11101D110101dddd101zE1000000") // VFPv2
// Floating-point system register access
INST(vfp_VMSR, "VMSR", "cccc111011100001tttt101000010000") // VFPv2
INST(vfp_VMRS, "VMRS", "cccc111011110001tttt101000010000") // VFPv2
// Extension register load-store instructions
INST(vfp_VPUSH, "VPUSH", "cccc11010D101101dddd101zvvvvvvvv") // VFPv2
INST(vfp_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv") // VFPv2
INST(vfp_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv") // VFPv2
INST(vfp_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv") // VFPv2
INST(vfp_VSTM_a1, "VSTM (A1)", "cccc110puDw0nnnndddd1011vvvvvvvv") // VFPv2
INST(vfp_VSTM_a2, "VSTM (A2)", "cccc110puDw0nnnndddd1010vvvvvvvv") // VFPv2
INST(vfp_VLDM_a1, "VLDM (A1)", "cccc110puDw1nnnndddd1011vvvvvvvv") // VFPv2
INST(vfp_VLDM_a2, "VLDM (A2)", "cccc110puDw1nnnndddd1010vvvvvvvv") // VFPv2

48
src/frontend/A32/decoder/vfp2.inc
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@ -1,48 +0,0 @@
// cccc1110________----101-__-0----
// Floating-point three-register data processing instructions
INST(vfp2_VMLA, "VMLA", "cccc11100D00nnnndddd101zN0M0mmmm")
INST(vfp2_VMLS, "VMLS", "cccc11100D00nnnndddd101zN1M0mmmm")
INST(vfp2_VNMLS, "VNMLS", "cccc11100D01nnnndddd101zN0M0mmmm")
INST(vfp2_VNMLA, "VNMLA", "cccc11100D01nnnndddd101zN1M0mmmm")
INST(vfp2_VMUL, "VMUL", "cccc11100D10nnnndddd101zN0M0mmmm")
INST(vfp2_VNMUL, "VNMUL", "cccc11100D10nnnndddd101zN1M0mmmm")
INST(vfp2_VADD, "VADD", "cccc11100D11nnnndddd101zN0M0mmmm")
INST(vfp2_VSUB, "VSUB", "cccc11100D11nnnndddd101zN1M0mmmm")
INST(vfp2_VDIV, "VDIV", "cccc11101D00nnnndddd101zN0M0mmmm")
// Floating-point move instructions
INST(vfp2_VMOV_u32_f64, "VMOV (core to f64)", "cccc11100000ddddtttt1011D0010000")
INST(vfp2_VMOV_f64_u32, "VMOV (f64 to core)", "cccc11100001nnnntttt1011N0010000")
INST(vfp2_VMOV_u32_f32, "VMOV (core to f32)", "cccc11100000nnnntttt1010N0010000")
INST(vfp2_VMOV_f32_u32, "VMOV (f32 to core)", "cccc11100001nnnntttt1010N0010000")
INST(vfp2_VMOV_2u32_2f32, "VMOV (2xcore to 2xf32)", "cccc11000100uuuutttt101000M1mmmm")
INST(vfp2_VMOV_2f32_2u32, "VMOV (2xf32 to 2xcore)", "cccc11000101uuuutttt101000M1mmmm")
INST(vfp2_VMOV_2u32_f64, "VMOV (2xcore to f64)", "cccc11000100uuuutttt101100M1mmmm")
INST(vfp2_VMOV_f64_2u32, "VMOV (f64 to 2xcore)", "cccc11000101uuuutttt101100M1mmmm")
INST(vfp2_VMOV_reg, "VMOV (reg)", "cccc11101D110000dddd101z01M0mmmm")
// Floating-point other instructions
INST(vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm")
INST(vfp2_VNEG, "VNEG", "cccc11101D110001dddd101z01M0mmmm")
INST(vfp2_VSQRT, "VSQRT", "cccc11101D110001dddd101z11M0mmmm")
INST(vfp2_VCVT_f_to_f, "VCVT (f32<->f64)", "cccc11101D110111dddd101z11M0mmmm")
INST(vfp2_VCVT_to_float, "VCVT (to float)", "cccc11101D111000dddd101zs1M0mmmm")
INST(vfp2_VCVT_to_u32, "VCVT (to u32)", "cccc11101D111100dddd101zr1M0mmmm")
INST(vfp2_VCVT_to_s32, "VCVT (to s32)", "cccc11101D111101dddd101zr1M0mmmm")
INST(vfp2_VCMP, "VCMP", "cccc11101D110100dddd101zE1M0mmmm")
INST(vfp2_VCMP_zero, "VCMP (with zero)", "cccc11101D110101dddd101zE1000000")
// Floating-point system register access
INST(vfp2_VMSR, "VMSR", "cccc111011100001tttt101000010000")
INST(vfp2_VMRS, "VMRS", "cccc111011110001tttt101000010000")
// Extension register load-store instructions
INST(vfp2_VPUSH, "VPUSH", "cccc11010D101101dddd101zvvvvvvvv")
INST(vfp2_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv")
INST(vfp2_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv")
INST(vfp2_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv")
INST(vfp2_VSTM_a1, "VSTM (A1)", "cccc110puDw0nnnndddd1011vvvvvvvv")
INST(vfp2_VSTM_a2, "VSTM (A2)", "cccc110puDw0nnnndddd1010vvvvvvvv")
INST(vfp2_VLDM_a1, "VLDM (A1)", "cccc110puDw1nnnndddd1011vvvvvvvv")
INST(vfp2_VLDM_a2, "VLDM (A2)", "cccc110puDw1nnnndddd1010vvvvvvvv")

78
src/frontend/A32/disassembler/disassembler_arm.cpp
View file

@ -14,7 +14,7 @@
#include "common/string_util.h" #include "common/string_util.h"
#include "frontend/imm.h" #include "frontend/imm.h"
#include "frontend/A32/decoder/arm.h" #include "frontend/A32/decoder/arm.h"
#include "frontend/A32/decoder/vfp2.h" #include "frontend/A32/decoder/vfp.h"
#include "frontend/A32/disassembler/disassembler.h" #include "frontend/A32/disassembler/disassembler.h"
#include "frontend/A32/types.h" #include "frontend/A32/types.h"
@ -1156,118 +1156,118 @@ public:
std::string arm_SRS() { return "ice"; } std::string arm_SRS() { return "ice"; }
// Floating point arithmetic instructions // Floating point arithmetic instructions
std::string vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vadd{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vadd{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vsub{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vsub{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vmul{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vmul{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vmla{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vmla{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vmls{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vmls{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vnmul{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vnmul{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vnmla{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vnmla{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vnmls{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vnmls{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { std::string vfp_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return fmt::format("vdiv{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); return fmt::format("vdiv{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D){ std::string vfp_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D){
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(true, Vd, D), t); return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(true, Vd, D), t);
} }
std::string vfp2_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N){ std::string vfp_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N){
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), t, FPRegStr(true, Vn, N)); return fmt::format("vmov{}.32 {}, {}", CondToString(cond), t, FPRegStr(true, Vn, N));
} }
std::string vfp2_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N){ std::string vfp_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N){
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(false, Vn, N), t); return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(false, Vn, N), t);
} }
std::string vfp2_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N){ std::string vfp_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N){
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), t, FPRegStr(false, Vn, N)); return fmt::format("vmov{}.32 {}, {}", CondToString(cond), t, FPRegStr(false, Vn, N));
} }
std::string vfp2_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ std::string vfp_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){
return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M), t, t2); return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M), t, t2);
} }
std::string vfp2_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ std::string vfp_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){
return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), t, t2, FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M)); return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), t, t2, FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M));
} }
std::string vfp2_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ std::string vfp_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm){
return fmt::format("vmov{} {}, {}, {}", CondToString(cond), FPRegStr(true, Vm, M), t, t2); return fmt::format("vmov{} {}, {}, {}", CondToString(cond), FPRegStr(true, Vm, M), t, t2);
} }
std::string vfp2_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ std::string vfp_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){
return fmt::format("vmov{} {}, {}, {}", CondToString(cond), t, t2, FPRegStr(true, Vm, M)); return fmt::format("vmov{} {}, {}, {}", CondToString(cond), t, t2, FPRegStr(true, Vm, M));
} }
std::string vfp2_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm){ std::string vfp_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm){
return fmt::format("vmov{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); return fmt::format("vmov{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { std::string vfp_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return fmt::format("vadd{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); return fmt::format("vadd{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { std::string vfp_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return fmt::format("vneg{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); return fmt::format("vneg{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { std::string vfp_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return fmt::format("vsqrt{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); return fmt::format("vsqrt{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { std::string vfp_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return fmt::format("vcvt{}.{}.{} {}, {}", CondToString(cond), !sz ? "f64" : "f32", sz ? "f64" : "f32", FPRegStr(!sz, Vd, D), FPRegStr(sz, Vm, M)); return fmt::format("vcvt{}.{}.{} {}, {}", CondToString(cond), !sz ? "f64" : "f32", sz ? "f64" : "f32", FPRegStr(!sz, Vd, D), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VCVT_to_float(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm) { std::string vfp_VCVT_to_float(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm) {
return fmt::format("vcvt{}.{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", is_signed ? "s32" : "u32", FPRegStr(sz, Vd, D), FPRegStr(false, Vm, M)); return fmt::format("vcvt{}.{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", is_signed ? "s32" : "u32", FPRegStr(sz, Vd, D), FPRegStr(false, Vm, M));
} }
std::string vfp2_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) { std::string vfp_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) {
return fmt::format("vcvt{}{}.u32.{} {}, {}", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D), FPRegStr(sz, Vm, M)); return fmt::format("vcvt{}{}.u32.{} {}, {}", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) { std::string vfp_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) {
return fmt::format("vcvt{}{}.s32.{} {}, {}", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D), FPRegStr(sz, Vm, M)); return fmt::format("vcvt{}{}.s32.{} {}, {}", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool E, bool M, size_t Vm) { std::string vfp_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool E, bool M, size_t Vm) {
return fmt::format("vcmp{}{}.{} {}, {}", E ? "e" : "", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); return fmt::format("vcmp{}{}.{} {}, {}", E ? "e" : "", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M));
} }
std::string vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, bool E) { std::string vfp_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, bool E) {
return fmt::format("vcmp{}{}.{} {}, #0.0", E ? "e" : "", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D)); return fmt::format("vcmp{}{}.{} {}, #0.0", E ? "e" : "", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D));
} }
std::string vfp2_VMSR(Cond cond, Reg t) { std::string vfp_VMSR(Cond cond, Reg t) {
return fmt::format("vmsr{} fpscr, {}", CondToString(cond), t); return fmt::format("vmsr{} fpscr, {}", CondToString(cond), t);
} }
std::string vfp2_VMRS(Cond cond, Reg t) { std::string vfp_VMRS(Cond cond, Reg t) {
if (t == Reg::R15) { if (t == Reg::R15) {
return fmt::format("vmrs{} apsr_nzcv, fpscr", CondToString(cond)); return fmt::format("vmrs{} apsr_nzcv, fpscr", CondToString(cond));
} else { } else {
@ -1275,33 +1275,33 @@ public:
} }
} }
std::string vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8) { std::string vfp_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8) {
return fmt::format("vpop{} {}(+{})", return fmt::format("vpop{} {}(+{})",
CondToString(cond), FPRegStr(sz, Vd, D), CondToString(cond), FPRegStr(sz, Vd, D),
imm8.ZeroExtend() >> (sz ? 1 : 0)); imm8.ZeroExtend() >> (sz ? 1 : 0));
} }
std::string vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8) { std::string vfp_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8) {
return fmt::format("vpush{} {}(+{})", return fmt::format("vpush{} {}(+{})",
CondToString(cond), FPRegStr(sz, Vd, D), CondToString(cond), FPRegStr(sz, Vd, D),
imm8.ZeroExtend() >> (sz ? 1 : 0)); imm8.ZeroExtend() >> (sz ? 1 : 0));
} }
std::string vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8) { std::string vfp_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8) {
const u32 imm32 = imm8.ZeroExtend() << 2; const u32 imm32 = imm8.ZeroExtend() << 2;
const char sign = U ? '+' : '-'; const char sign = U ? '+' : '-';
return fmt::format("vldr{} {}, [{}, #{}{}]", return fmt::format("vldr{} {}, [{}, #{}{}]",
CondToString(cond), FPRegStr(sz, Vd, D), n, sign, imm32); CondToString(cond), FPRegStr(sz, Vd, D), n, sign, imm32);
} }
std::string vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8) { std::string vfp_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8) {
const u32 imm32 = imm8.ZeroExtend() << 2; const u32 imm32 = imm8.ZeroExtend() << 2;
const char sign = U ? '+' : '-'; const char sign = U ? '+' : '-';
return fmt::format("vstr{} {}, [{}, #{}{}]", return fmt::format("vstr{} {}, [{}, #{}{}]",
CondToString(cond), FPRegStr(sz, Vd, D), n, sign, imm32); CondToString(cond), FPRegStr(sz, Vd, D), n, sign, imm32);
} }
std::string vfp2_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { std::string vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
const char* mode = "<invalid mode>"; const char* mode = "<invalid mode>";
if (!p && u) { if (!p && u) {
mode = "ia"; mode = "ia";
@ -1314,7 +1314,7 @@ public:
FPRegStr(true, Vd, D), imm8.ZeroExtend()); FPRegStr(true, Vd, D), imm8.ZeroExtend());
} }
std::string vfp2_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { std::string vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
const char* mode = "<invalid mode>"; const char* mode = "<invalid mode>";
if (!p && u) { if (!p && u) {
mode = "ia"; mode = "ia";
@ -1327,7 +1327,7 @@ public:
FPRegStr(false, Vd, D), imm8.ZeroExtend()); FPRegStr(false, Vd, D), imm8.ZeroExtend());
} }
std::string vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { std::string vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
const char* mode = "<invalid mode>"; const char* mode = "<invalid mode>";
if (!p && u) { if (!p && u) {
mode = "ia"; mode = "ia";
@ -1340,7 +1340,7 @@ public:
FPRegStr(true, Vd, D), imm8.ZeroExtend()); FPRegStr(true, Vd, D), imm8.ZeroExtend());
} }
std::string vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { std::string vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
const char* mode = "<invalid mode>"; const char* mode = "<invalid mode>";
if (!p && u) { if (!p && u) {
mode = "ia"; mode = "ia";
@ -1356,7 +1356,7 @@ public:
std::string DisassembleArm(u32 instruction) { std::string DisassembleArm(u32 instruction) {
DisassemblerVisitor visitor; DisassemblerVisitor visitor;
if (auto vfp_decoder = DecodeVFP2<DisassemblerVisitor>(instruction)) { if (auto vfp_decoder = DecodeVFP<DisassemblerVisitor>(instruction)) {
return vfp_decoder->get().call(visitor, instruction); return vfp_decoder->get().call(visitor, instruction);
} else if (auto decoder = DecodeArm<DisassemblerVisitor>(instruction)) { } else if (auto decoder = DecodeArm<DisassemblerVisitor>(instruction)) {
return decoder->get().call(visitor, instruction); return decoder->get().call(visitor, instruction);

6
src/frontend/A32/translate/translate_arm.cpp
View file

@ -9,7 +9,7 @@
#include "common/assert.h" #include "common/assert.h"
#include "dynarmic/A32/config.h" #include "dynarmic/A32/config.h"
#include "frontend/A32/decoder/arm.h" #include "frontend/A32/decoder/arm.h"
#include "frontend/A32/decoder/vfp2.h" #include "frontend/A32/decoder/vfp.h"
#include "frontend/A32/location_descriptor.h" #include "frontend/A32/location_descriptor.h"
#include "frontend/A32/translate/translate.h" #include "frontend/A32/translate/translate.h"
#include "frontend/A32/translate/translate_arm/translate_arm.h" #include "frontend/A32/translate/translate_arm/translate_arm.h"
@ -37,7 +37,7 @@ IR::Block TranslateArm(LocationDescriptor descriptor, MemoryReadCodeFuncType mem
const u32 arm_pc = visitor.ir.current_location.PC(); const u32 arm_pc = visitor.ir.current_location.PC();
const u32 arm_instruction = memory_read_code(arm_pc); const u32 arm_instruction = memory_read_code(arm_pc);
if (const auto vfp_decoder = DecodeVFP2<ArmTranslatorVisitor>(arm_instruction)) { if (const auto vfp_decoder = DecodeVFP<ArmTranslatorVisitor>(arm_instruction)) {
should_continue = vfp_decoder->get().call(visitor, arm_instruction); should_continue = vfp_decoder->get().call(visitor, arm_instruction);
} else if (const auto decoder = DecodeArm<ArmTranslatorVisitor>(arm_instruction)) { } else if (const auto decoder = DecodeArm<ArmTranslatorVisitor>(arm_instruction)) {
should_continue = decoder->get().call(visitor, arm_instruction); should_continue = decoder->get().call(visitor, arm_instruction);
@ -72,7 +72,7 @@ bool TranslateSingleArmInstruction(IR::Block& block, LocationDescriptor descript
// TODO: Proper cond handling // TODO: Proper cond handling
bool should_continue = true; bool should_continue = true;
if (const auto vfp_decoder = DecodeVFP2<ArmTranslatorVisitor>(arm_instruction)) { if (const auto vfp_decoder = DecodeVFP<ArmTranslatorVisitor>(arm_instruction)) {
should_continue = vfp_decoder->get().call(visitor, arm_instruction); should_continue = vfp_decoder->get().call(visitor, arm_instruction);
} else if (const auto decoder = DecodeArm<ArmTranslatorVisitor>(arm_instruction)) { } else if (const auto decoder = DecodeArm<ArmTranslatorVisitor>(arm_instruction)) {
should_continue = decoder->get().call(visitor, arm_instruction); should_continue = decoder->get().call(visitor, arm_instruction);

74
src/frontend/A32/translate/translate_arm/translate_arm.h
View file

@ -358,51 +358,51 @@ struct ArmTranslatorVisitor final {
bool arm_SRS(); bool arm_SRS();
// Floating-point three-register data processing instructions // Floating-point three-register data processing instructions
bool vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); bool vfp_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
// Floating-point move instructions // Floating-point move instructions
bool vfp2_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D); bool vfp_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D);
bool vfp2_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N); bool vfp_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N);
bool vfp2_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N); bool vfp_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N);
bool vfp2_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N); bool vfp_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N);
bool vfp2_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm); bool vfp_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm);
bool vfp2_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm); bool vfp_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm);
bool vfp2_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm); bool vfp_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm);
bool vfp2_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm); bool vfp_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm);
bool vfp2_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
// Floating-point misc instructions // Floating-point misc instructions
bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VCVT_to_float(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm); bool vfp_VCVT_to_float(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm);
bool vfp2_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm); bool vfp_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm);
bool vfp2_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm); bool vfp_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm);
bool vfp2_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool E, bool M, size_t Vm); bool vfp_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool E, bool M, size_t Vm);
bool vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, bool E); bool vfp_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, bool E);
// Floating-point system register access // Floating-point system register access
bool vfp2_VMSR(Cond cond, Reg t); bool vfp_VMSR(Cond cond, Reg t);
bool vfp2_VMRS(Cond cond, Reg t); bool vfp_VMRS(Cond cond, Reg t);
// Floating-point load-store instructions // Floating-point load-store instructions
bool vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8); bool vfp_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8);
bool vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8); bool vfp_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8);
bool vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8); bool vfp_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8);
bool vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8); bool vfp_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8);
bool vfp2_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8); bool vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8);
bool vfp2_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8); bool vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8);
bool vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8); bool vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8);
bool vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8); bool vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8);
}; };
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

74
src/frontend/A32/translate/translate_arm/vfp2.cpp → src/frontend/A32/translate/translate_arm/vfp.cpp
View file

@ -92,7 +92,7 @@ bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg m, c
// VADD<c>.F64 <Dd>, <Dn>, <Dm> // VADD<c>.F64 <Dd>, <Dn>, <Dm>
// VADD<c>.F32 <Sd>, <Sn>, <Sm> // VADD<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -111,7 +111,7 @@ bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bo
// VSUB<c>.F64 <Dd>, <Dn>, <Dm> // VSUB<c>.F64 <Dd>, <Dn>, <Dm>
// VSUB<c>.F32 <Sd>, <Sn>, <Sm> // VSUB<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -130,7 +130,7 @@ bool ArmTranslatorVisitor::vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bo
// VMUL<c>.F64 <Dd>, <Dn>, <Dm> // VMUL<c>.F64 <Dd>, <Dn>, <Dm>
// VMUL<c>.F32 <Sd>, <Sn>, <Sm> // VMUL<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -149,7 +149,7 @@ bool ArmTranslatorVisitor::vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bo
// VMLA<c>.F64 <Dd>, <Dn>, <Dm> // VMLA<c>.F64 <Dd>, <Dn>, <Dm>
// VMLA<c>.F32 <Sd>, <Sn>, <Sm> // VMLA<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -169,7 +169,7 @@ bool ArmTranslatorVisitor::vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bo
// VMLS<c>.F64 <Dd>, <Dn>, <Dm> // VMLS<c>.F64 <Dd>, <Dn>, <Dm>
// VMLS<c>.F32 <Sd>, <Sn>, <Sm> // VMLS<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -189,7 +189,7 @@ bool ArmTranslatorVisitor::vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bo
// VNMUL<c>.F64 <Dd>, <Dn>, <Dm> // VNMUL<c>.F64 <Dd>, <Dn>, <Dm>
// VNMUL<c>.F32 <Sd>, <Sn>, <Sm> // VNMUL<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -208,7 +208,7 @@ bool ArmTranslatorVisitor::vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, b
// VNMLA<c>.F64 <Dd>, <Dn>, <Dm> // VNMLA<c>.F64 <Dd>, <Dn>, <Dm>
// VNMLA<c>.F32 <Sd>, <Sn>, <Sm> // VNMLA<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -228,7 +228,7 @@ bool ArmTranslatorVisitor::vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, b
// VNMLS<c>.F64 <Dd>, <Dn>, <Dm> // VNMLS<c>.F64 <Dd>, <Dn>, <Dm>
// VNMLS<c>.F32 <Sd>, <Sn>, <Sm> // VNMLS<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -248,7 +248,7 @@ bool ArmTranslatorVisitor::vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, b
// VDIV<c>.F64 <Dd>, <Dn>, <Dm> // VDIV<c>.F64 <Dd>, <Dn>, <Dm>
// VDIV<c>.F32 <Sd>, <Sn>, <Sm> // VDIV<c>.F32 <Sd>, <Sn>, <Sm>
bool ArmTranslatorVisitor::vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -266,7 +266,7 @@ bool ArmTranslatorVisitor::vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bo
} }
// VMOV<c>.32 <Dd[0]>, <Rt> // VMOV<c>.32 <Dd[0]>, <Rt>
bool ArmTranslatorVisitor::vfp2_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D) { bool ArmTranslatorVisitor::vfp_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D) {
if (t == Reg::PC) { if (t == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
} }
@ -285,7 +285,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D
} }
// VMOV<c>.32 <Rt>, <Dn[0]> // VMOV<c>.32 <Rt>, <Dn[0]>
bool ArmTranslatorVisitor::vfp2_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N) { bool ArmTranslatorVisitor::vfp_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N) {
if (t == Reg::PC) { if (t == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
} }
@ -301,7 +301,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N
} }
// VMOV<c> <Sn>, <Rt> // VMOV<c> <Sn>, <Rt>
bool ArmTranslatorVisitor::vfp2_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N) { bool ArmTranslatorVisitor::vfp_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N) {
if (t == Reg::PC) { if (t == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
} }
@ -316,7 +316,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N
} }
// VMOV<c> <Rt>, <Sn> // VMOV<c> <Rt>, <Sn>
bool ArmTranslatorVisitor::vfp2_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N) { bool ArmTranslatorVisitor::vfp_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N) {
if (t == Reg::PC) { if (t == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
} }
@ -331,7 +331,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N
} }
// VMOV<c> <Sm>, <Sm1>, <Rt>, <Rt2> // VMOV<c> <Sm>, <Sm1>, <Rt>, <Rt2>
bool ArmTranslatorVisitor::vfp2_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) {
const auto m = ToExtReg(false, Vm, M); const auto m = ToExtReg(false, Vm, M);
if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31) { if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31) {
return UnpredictableInstruction(); return UnpredictableInstruction();
@ -347,7 +347,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M,
} }
// VMOV<c> <Rt>, <Rt2>, <Sm>, <Sm1> // VMOV<c> <Rt>, <Rt2>, <Sm>, <Sm1>
bool ArmTranslatorVisitor::vfp2_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) {
const auto m = ToExtReg(false, Vm, M); const auto m = ToExtReg(false, Vm, M);
if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31) { if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31) {
return UnpredictableInstruction(); return UnpredictableInstruction();
@ -367,7 +367,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M,
} }
// VMOV<c> <Dm>, <Rt>, <Rt2> // VMOV<c> <Dm>, <Rt>, <Rt2>
bool ArmTranslatorVisitor::vfp2_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm) {
const auto m = ToExtReg(true, Vm, M); const auto m = ToExtReg(true, Vm, M);
if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31) { if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31) {
return UnpredictableInstruction(); return UnpredictableInstruction();
@ -383,7 +383,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M,
} }
// VMOV<c> <Rt>, <Rt2>, <Dm> // VMOV<c> <Rt>, <Rt2>, <Dm>
bool ArmTranslatorVisitor::vfp2_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) {
const auto m = ToExtReg(true, Vm, M); const auto m = ToExtReg(true, Vm, M);
if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31) { if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31) {
return UnpredictableInstruction(); return UnpredictableInstruction();
@ -405,7 +405,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M,
// VMOV<c>.F64 <Dd>, <Dm> // VMOV<c>.F64 <Dd>, <Dm>
// VMOV<c>.F32 <Sd>, <Sm> // VMOV<c>.F32 <Sd>, <Sm>
bool ArmTranslatorVisitor::vfp2_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -420,7 +420,7 @@ bool ArmTranslatorVisitor::vfp2_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz,
// VABS<c>.F64 <Dd>, <Dm> // VABS<c>.F64 <Dd>, <Dm>
// VABS<c>.F32 <Sd>, <Sm> // VABS<c>.F32 <Sd>, <Sm>
bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -437,7 +437,7 @@ bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool
// VNEG<c>.F64 <Dd>, <Dm> // VNEG<c>.F64 <Dd>, <Dm>
// VNEG<c>.F32 <Sd>, <Sm> // VNEG<c>.F32 <Sd>, <Sm>
bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -454,7 +454,7 @@ bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool
// VSQRT<c>.F64 <Dd>, <Dm> // VSQRT<c>.F64 <Dd>, <Dm>
// VSQRT<c>.F32 <Sd>, <Sm> // VSQRT<c>.F32 <Sd>, <Sm>
bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -471,7 +471,7 @@ bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, boo
// VCVT<c>.F64.F32 <Dd>, <Sm> // VCVT<c>.F64.F32 <Dd>, <Sm>
// VCVT<c>.F32.F64 <Sd>, <Dm> // VCVT<c>.F32.F64 <Sd>, <Dm>
bool ArmTranslatorVisitor::vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -494,7 +494,7 @@ bool ArmTranslatorVisitor::vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool s
// VCVT.F32.{S32,U32} <Sd>, <Sm> // VCVT.F32.{S32,U32} <Sd>, <Sm>
// VCVT.F64.{S32,U32} <Sd>, <Dm> // VCVT.F64.{S32,U32} <Sd>, <Dm>
bool ArmTranslatorVisitor::vfp2_VCVT_to_float(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VCVT_to_float(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -521,7 +521,7 @@ bool ArmTranslatorVisitor::vfp2_VCVT_to_float(Cond cond, bool D, size_t Vd, bool
// VCVT{,R}.U32.F32 <Sd>, <Sm> // VCVT{,R}.U32.F32 <Sd>, <Sm>
// VCVT{,R}.U32.F64 <Sd>, <Dm> // VCVT{,R}.U32.F64 <Sd>, <Dm>
bool ArmTranslatorVisitor::vfp2_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -537,7 +537,7 @@ bool ArmTranslatorVisitor::vfp2_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool s
// VCVT{,R}.S32.F32 <Sd>, <Sm> // VCVT{,R}.S32.F32 <Sd>, <Sm>
// VCVT{,R}.S32.F64 <Sd>, <Dm> // VCVT{,R}.S32.F64 <Sd>, <Dm>
bool ArmTranslatorVisitor::vfp2_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -553,7 +553,7 @@ bool ArmTranslatorVisitor::vfp2_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool s
// VCMP{E}.F32 <Sd>, <Sm> // VCMP{E}.F32 <Sd>, <Sm>
// VCMP{E}.F64 <Dd>, <Dm> // VCMP{E}.F64 <Dd>, <Dm>
bool ArmTranslatorVisitor::vfp2_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool E, bool M, size_t Vm) { bool ArmTranslatorVisitor::vfp_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool E, bool M, size_t Vm) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -571,7 +571,7 @@ bool ArmTranslatorVisitor::vfp2_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool
// VCMP{E}.F32 <Sd>, #0.0 // VCMP{E}.F32 <Sd>, #0.0
// VCMP{E}.F64 <Dd>, #0.0 // VCMP{E}.F64 <Dd>, #0.0
bool ArmTranslatorVisitor::vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, bool E) { bool ArmTranslatorVisitor::vfp_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, bool E) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -592,7 +592,7 @@ bool ArmTranslatorVisitor::vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz,
} }
// VMSR FPSCR, <Rt> // VMSR FPSCR, <Rt>
bool ArmTranslatorVisitor::vfp2_VMSR(Cond cond, Reg t) { bool ArmTranslatorVisitor::vfp_VMSR(Cond cond, Reg t) {
if (t == Reg::PC) { if (t == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
} }
@ -611,7 +611,7 @@ bool ArmTranslatorVisitor::vfp2_VMSR(Cond cond, Reg t) {
} }
// VMRS <Rt>, FPSCR // VMRS <Rt>, FPSCR
bool ArmTranslatorVisitor::vfp2_VMRS(Cond cond, Reg t) { bool ArmTranslatorVisitor::vfp_VMRS(Cond cond, Reg t) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -628,7 +628,7 @@ bool ArmTranslatorVisitor::vfp2_VMRS(Cond cond, Reg t) {
} }
// VPOP.{F32,F64} <list> // VPOP.{F32,F64} <list>
bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8) { bool ArmTranslatorVisitor::vfp_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8) {
const ExtReg d = ToExtReg(sz, Vd, D); const ExtReg d = ToExtReg(sz, Vd, D);
const size_t regs = sz ? imm8.ZeroExtend() >> 1 : imm8.ZeroExtend(); const size_t regs = sz ? imm8.ZeroExtend() >> 1 : imm8.ZeroExtend();
@ -668,7 +668,7 @@ bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<
} }
// VPUSH.{F32,F64} <list> // VPUSH.{F32,F64} <list>
bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8) { bool ArmTranslatorVisitor::vfp_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm<8> imm8) {
const ExtReg d = ToExtReg(sz, Vd, D); const ExtReg d = ToExtReg(sz, Vd, D);
const size_t regs = sz ? imm8.ZeroExtend() >> 1 : imm8.ZeroExtend(); const size_t regs = sz ? imm8.ZeroExtend() >> 1 : imm8.ZeroExtend();
@ -709,7 +709,7 @@ bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm
// VLDR<c> <Dd>, [<Rn>{, #+/-<imm>}] // VLDR<c> <Dd>, [<Rn>{, #+/-<imm>}]
// VLDR<c> <Sd>, [<Rn>{, #+/-<imm>}] // VLDR<c> <Sd>, [<Rn>{, #+/-<imm>}]
bool ArmTranslatorVisitor::vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8) { bool ArmTranslatorVisitor::vfp_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -735,7 +735,7 @@ bool ArmTranslatorVisitor::vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd
// VSTR<c> <Dd>, [<Rn>{, #+/-<imm>}] // VSTR<c> <Dd>, [<Rn>{, #+/-<imm>}]
// VSTR<c> <Sd>, [<Rn>{, #+/-<imm>}] // VSTR<c> <Sd>, [<Rn>{, #+/-<imm>}]
bool ArmTranslatorVisitor::vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8) { bool ArmTranslatorVisitor::vfp_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm<8> imm8) {
if (!ConditionPassed(cond)) { if (!ConditionPassed(cond)) {
return true; return true;
} }
@ -761,7 +761,7 @@ bool ArmTranslatorVisitor::vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd
} }
// VSTM{mode}<c> <Rn>{!}, <list of double registers> // VSTM{mode}<c> <Rn>{!}, <list of double registers>
bool ArmTranslatorVisitor::vfp2_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { bool ArmTranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
if (!p && !u && !w) { if (!p && !u && !w) {
ASSERT_MSG(false, "Decode error"); ASSERT_MSG(false, "Decode error");
} }
@ -813,7 +813,7 @@ bool ArmTranslatorVisitor::vfp2_VSTM_a1(Cond cond, bool p, bool u, bool D, bool
} }
// VSTM{mode}<c> <Rn>{!}, <list of single registers> // VSTM{mode}<c> <Rn>{!}, <list of single registers>
bool ArmTranslatorVisitor::vfp2_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { bool ArmTranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
if (!p && !u && !w) { if (!p && !u && !w) {
ASSERT_MSG(false, "Decode error"); ASSERT_MSG(false, "Decode error");
} }
@ -856,7 +856,7 @@ bool ArmTranslatorVisitor::vfp2_VSTM_a2(Cond cond, bool p, bool u, bool D, bool
} }
// VLDM{mode}<c> <Rn>{!}, <list of double registers> // VLDM{mode}<c> <Rn>{!}, <list of double registers>
bool ArmTranslatorVisitor::vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { bool ArmTranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
if (!p && !u && !w) { if (!p && !u && !w) {
ASSERT_MSG(false, "Decode error"); ASSERT_MSG(false, "Decode error");
} }
@ -906,7 +906,7 @@ bool ArmTranslatorVisitor::vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool
} }
// VLDM{mode}<c> <Rn>{!}, <list of single registers> // VLDM{mode}<c> <Rn>{!}, <list of single registers>
bool ArmTranslatorVisitor::vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { bool ArmTranslatorVisitor::vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
if (!p && !u && !w) { if (!p && !u && !w) {
ASSERT_MSG(false, "Decode error"); ASSERT_MSG(false, "Decode error");
} }

2
tests/A32/fuzz_arm.cpp
View file

@ -78,7 +78,7 @@ u32 GenRandomInst(u32 pc, bool is_last_inst) {
const std::vector<std::tuple<std::string, const char*>> list { const std::vector<std::tuple<std::string, const char*>> list {
#define INST(fn, name, bitstring) {#fn, bitstring}, #define INST(fn, name, bitstring) {#fn, bitstring},
#include "frontend/A32/decoder/arm.inc" #include "frontend/A32/decoder/arm.inc"
#include "frontend/A32/decoder/vfp2.inc" #include "frontend/A32/decoder/vfp.inc"
#undef INST #undef INST
}; };