A64: Implement TRN1
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2 changed files with 37 additions and 1 deletions
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@ -515,7 +515,7 @@ INST(USRA_1, "USRA", "01111
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// Data Processing - FP and SIMD - SIMD Permute
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// Data Processing - FP and SIMD - SIMD Permute
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//INST(UZP1, "UZP1", "0Q001110zz0mmmmm000110nnnnnddddd")
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//INST(UZP1, "UZP1", "0Q001110zz0mmmmm000110nnnnnddddd")
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//INST(TRN1, "TRN1", "0Q001110zz0mmmmm001010nnnnnddddd")
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INST(TRN1, "TRN1", "0Q001110zz0mmmmm001010nnnnnddddd")
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INST(ZIP1, "ZIP1", "0Q001110zz0mmmmm001110nnnnnddddd")
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INST(ZIP1, "ZIP1", "0Q001110zz0mmmmm001110nnnnnddddd")
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//INST(UZP2, "UZP2", "0Q001110zz0mmmmm010110nnnnnddddd")
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//INST(UZP2, "UZP2", "0Q001110zz0mmmmm010110nnnnnddddd")
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//INST(TRN2, "TRN2", "0Q001110zz0mmmmm011010nnnnnddddd")
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//INST(TRN2, "TRN2", "0Q001110zz0mmmmm011010nnnnnddddd")
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@ -8,6 +8,42 @@
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namespace Dynarmic::A64 {
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::TRN1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (!Q && size == 0b11) {
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return ReservedValue();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << size.ZeroExtend();
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const IR::U128 m = V(datasize, Vm);
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const IR::U128 n = V(datasize, Vn);
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const IR::U128 result = [&] {
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switch (esize) {
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case 8:
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case 16:
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case 32: {
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// Create a mask of elements we care about (e.g. for 8-bit 0x00FF00FF00FF00FF)
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const u64 mask_element = Common::Ones<u64>(esize);
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const u64 mask_value = Common::Replicate<u64>(mask_element, esize * 2);
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const IR::U128 mask = ir.VectorBroadcast(64, I(64, mask_value));
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const IR::U128 anded_m = ir.VectorAnd(m, mask);
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const IR::U128 anded_n = ir.VectorAnd(n, mask);
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return ir.VectorOr(ir.VectorLogicalShiftLeft(esize * 2, anded_m, esize), anded_n);
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}
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case 64: {
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default:
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return ir.VectorSetElement(esize, n, 1, ir.VectorGetElement(esize, m, 0));
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}
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}
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}();
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::ZIP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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bool TranslatorVisitor::ZIP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) {
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if (size == 0b11 && !Q) {
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return ReservedValue();
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return ReservedValue();
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