vfp: Implement vectorized VFP instructions
This commit is contained in:
MerryMage
parent
f2dd82967f
commit
358cf7c322
2 changed files with 175 additions and 113 deletions
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@ -65,6 +65,8 @@ struct ArmTranslatorVisitor final {
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IR::IREmitter::ResultAndCarry EmitImmShift(IR::Value value, ShiftType type, Imm5 imm5, IR::Value carry_in);
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IR::IREmitter::ResultAndCarry EmitRegShift(IR::Value value, ShiftType type, IR::Value amount, IR::Value carry_in);
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IR::Value SignZeroExtendRor(Reg m, SignExtendRotation rotate);
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template <typename FnT> bool EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtReg m, const FnT& fn);
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template <typename FnT> bool EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg m, const FnT& fn);
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// Branch instructions
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bool arm_B(Cond cond, Imm24 imm24);
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@ -17,177 +17,241 @@ static ExtReg ToExtReg(bool sz, size_t base, bool bit) {
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}
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}
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bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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template <typename FnT>
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bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtReg m, const FnT& fn) {
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// VFP register banks are 8 single-precision registers in size.
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const size_t register_bank_size = sz ? 4 : 8;
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if (!ir.current_location.FPSCR().Stride()) {
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return UnpredictableInstruction();
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}
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size_t vector_length = ir.current_location.FPSCR().Len();
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size_t vector_stride = *ir.current_location.FPSCR().Stride();
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// Unpredictable case
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if (vector_stride * vector_length > register_bank_size) {
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return UnpredictableInstruction();
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}
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// Scalar case
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if (vector_length == 1) {
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if (vector_stride != 1)
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return UnpredictableInstruction();
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fn(d, n, m);
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return true;
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}
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// The VFP register file is divided into banks each containing:
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// * eight single-precision registers, or
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// * four double-precision reigsters.
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// VFP vector instructions access these registers in a circular manner.
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const auto bank_increment = [register_bank_size](ExtReg reg, size_t stride) -> ExtReg {
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size_t reg_number = static_cast<size_t>(reg);
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size_t bank_index = reg_number % register_bank_size;
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size_t bank_start = reg_number - bank_index;
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size_t next_reg_number = bank_start + ((bank_index + stride) % register_bank_size);
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return static_cast<ExtReg>(next_reg_number);
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};
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// The first and fifth banks in the register file are scalar banks.
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// All the other banks are vector banks.
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const auto belongs_to_scalar_bank = [](ExtReg reg) -> bool {
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return (reg >= ExtReg::D0 && reg <= ExtReg::D3)
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|| (reg >= ExtReg::D16 && reg <= ExtReg::D19)
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|| (reg >= ExtReg::S0 && reg <= ExtReg::S7);
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};
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const bool d_is_scalar = belongs_to_scalar_bank(d);
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const bool m_is_scalar = belongs_to_scalar_bank(m);
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if (d_is_scalar) {
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// If destination register is in a scalar bank, the operands and results are all scalars.
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vector_length = 1;
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}
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for (size_t i = 0; i < vector_length; i++) {
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fn(d, n, m);
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d = bank_increment(d, vector_stride);
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n = bank_increment(n, vector_stride);
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if (!m_is_scalar)
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m = bank_increment(m, vector_stride);
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}
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return true;
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}
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template <typename FnT>
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bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg m, const FnT& fn) {
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return EmitVfpVectorOperation(sz, d, ExtReg::S0, m, [fn](ExtReg d, ExtReg, ExtReg m){
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fn(d, m);
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});
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}
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bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VADD.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPAdd64(reg_n, reg_m, true)
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: ir.FPAdd32(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPAdd64(reg_n, reg_m, true)
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: ir.FPAdd32(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VSUB.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPSub64(reg_n, reg_m, true)
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: ir.FPSub32(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPSub64(reg_n, reg_m, true)
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: ir.FPSub32(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VMUL.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPMul64(reg_n, reg_m, true)
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: ir.FPMul32(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPMul64(reg_n, reg_m, true)
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: ir.FPMul32(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VMLA.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = sz
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? ir.FPAdd64(reg_d, ir.FPMul64(reg_n, reg_m, true), true)
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: ir.FPAdd32(reg_d, ir.FPMul32(reg_n, reg_m, true), true);
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = sz
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? ir.FPAdd64(reg_d, ir.FPMul64(reg_n, reg_m, true), true)
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: ir.FPAdd32(reg_d, ir.FPMul32(reg_n, reg_m, true), true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VMLS.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = sz
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? ir.FPAdd64(reg_d, ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true)
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: ir.FPAdd32(reg_d, ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true);
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = sz
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? ir.FPAdd64(reg_d, ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true)
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: ir.FPAdd32(reg_d, ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VNMUL.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true))
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: ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true));
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true))
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: ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true));
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VNMLA.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = sz
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? ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true)
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: ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true);
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = sz
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? ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true)
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: ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VNMLS.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = sz
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? ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPMul64(reg_n, reg_m, true), true)
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: ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPMul32(reg_n, reg_m, true), true);
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = sz
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? ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPMul64(reg_n, reg_m, true), true)
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: ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPMul32(reg_n, reg_m, true), true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VDIV.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPDiv64(reg_n, reg_m, true)
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: ir.FPDiv32(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPDiv64(reg_n, reg_m, true)
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: ir.FPDiv32(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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@ -297,65 +361,61 @@ bool ArmTranslatorVisitor::vfp2_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M,
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VMOV.{F32,F64} <{S,D}d>, <{S,D}m>
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if (ConditionPassed(cond)) {
|
||||
ir.SetExtendedRegister(d, ir.GetExtendedRegister(m));
|
||||
return EmitVfpVectorOperation(sz, d, m, [this](ExtReg d, ExtReg m) {
|
||||
ir.SetExtendedRegister(d, ir.GetExtendedRegister(m));
|
||||
});
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
|
||||
if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
|
||||
return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
|
||||
|
||||
ExtReg d = ToExtReg(sz, Vd, D);
|
||||
ExtReg m = ToExtReg(sz, Vm, M);
|
||||
// VABS.{F32,F64} <{S,D}d>, <{S,D}m>
|
||||
if (ConditionPassed(cond)) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPAbs64(reg_m)
|
||||
: ir.FPAbs32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
return EmitVfpVectorOperation(sz, d, m, [sz, this](ExtReg d, ExtReg m) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPAbs64(reg_m)
|
||||
: ir.FPAbs32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
});
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
|
||||
if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
|
||||
return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
|
||||
|
||||
ExtReg d = ToExtReg(sz, Vd, D);
|
||||
ExtReg m = ToExtReg(sz, Vm, M);
|
||||
// VNEG.{F32,F64} <{S,D}d>, <{S,D}m>
|
||||
if (ConditionPassed(cond)) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPNeg64(reg_m)
|
||||
: ir.FPNeg32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
return EmitVfpVectorOperation(sz, d, m, [sz, this](ExtReg d, ExtReg m) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPNeg64(reg_m)
|
||||
: ir.FPNeg32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
});
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
|
||||
if (ir.current_location.FPSCR().Len() != 1 || ir.current_location.FPSCR().Stride() != boost::optional<size_t>{1})
|
||||
return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
|
||||
|
||||
ExtReg d = ToExtReg(sz, Vd, D);
|
||||
ExtReg m = ToExtReg(sz, Vm, M);
|
||||
// VSQRT.{F32,F64} <{S,D}d>, <{S,D}m>
|
||||
if (ConditionPassed(cond)) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPSqrt64(reg_m)
|
||||
: ir.FPSqrt32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
return EmitVfpVectorOperation(sz, d, m, [sz, this](ExtReg d, ExtReg m) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPSqrt64(reg_m)
|
||||
: ir.FPSqrt32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
});
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue